John McGee wrote:
>
> G'day Technetters-
>
> I'd like to 'springboard' from what Mark Weiler wrote, way back on
> Thursday, October 10, 1996 :
>
> > We are building a board that has 8 layers with multiple ground
> planes...
> > making it difficult to optimize the wave solder profile to get 100%
> fill...
> > ... on the top side of the board.
> >
> > The IPC A-610 rev B specification calls out 75% fill as being
> acceptable
> > (table 4-1, pg. 52) on through hole solder joints....
> >
> > Is a solder joint that is 75% filled over the wave stronger (more
> reliable)
> > than a solder joint that has been touched up to get to 100% with a
> fillet?
> >
> > What is the effect to long term reliability of touching up a through
> hole
> > solder joint?
> >
> > I would really like some reference material on this subject if anyone
> has
> > a source.
> >
> > Thanks,
> >
> > Mark Weiler
> > [log in to unmask]
> > 512-728-8323
> >******************
>
> The questions raised have been bugging me for a while, too. And some
> from a slightly different perspective, as well...
>
> IPC-A-610B, Table 4-1 calls out 75% fill as the minimum acceptable condition
>
> for class 3 assemblies. If Class 2, however, would it be appropriate to
> apply
> the exception of Fig. 4-2, when internal conductive layers are involved?
> Or is it incorrect to assess any of the internal layers as corresponding to
> the
> heatsink plane unless one of those layers is specifically called out as
> such?
>
> At some point, it seems, the internal (non-"heatsink") layers will introduce
>
> the cumulative effects comparable to those introduced by a heatsink plane.
> Is it expected that solder process modifications can and should be varied
> to accomodate any number of current carrying layers and still accomplish
> the required fill?
>
> Is "fill" is merely a visual indicator of the wetting success and the
> integrity of
> the PTH, or is there something less obvious to this requirement?
>
> Or am I missing something...like *the point entirely* ?
>
> Thanks for any and all help! (And, Mark - thanks for the boost.)
>
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John,
1. "HOLE FILL" definitely is a good indicator of PTH solderability and
PTH RELIABILITY which is more critical.
2. Normally a PTH during wave should fill unless there are problems like:
a) Plating void in barrel copper
b) outgassing from laminate through cu voids
c) Contamination on barrel wall and or component lead
d) Heavy oxidation of plated copper and or component lead
e) delamination at IP layers
f) Laminate voids with wedged copper plating
If PTH does not fill due to a) - f), then there is going to be serious
relaibility problem.
3. A touched up PTH to remove solder voids is WORSE than the orginal PTH.
4. Some voids are OK and should not affect PTH reliability except if the
cause of the voids is a) - f).
This has been discussed in many papers over the years. Search in
CIRCUIT WORLD for many good articles, 1986-1993 by C Lea et al.
--
Pratap Singh
Tel./Fax: 512-255-6820
e-mail: [log in to unmask]
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