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December 2001

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Subject:
From:
Yehuda Weisz <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Thu, 27 Dec 2001 12:14:19 +0200
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Hi Adam,
If I understand, you mean to ask: "How long should it take to create the first ppms of a full conductive copper layer inside the PTH?" (something like that - how long untill the whole hole wall gets the "good" conductivity of copper).
I cannot relate specifically to Blackhole since I work with SHADOW, but I think the answer is really not that straight forward, as Rudy implied.
In general I can tell you that the creation of this "first conductive layer" does take relativly considerable time compared to electroless copper. This time depends on many factors, starting with the conductivity of the direct metallization layer, the diameter of the via, the Aspect ratio (I did mention the latter two separately in purpose), the actual current density, the agitaion and more.
If you want to get some approximation of this time dependency of plating, I would advise you to create an artwork of a mesh that has diffrent square sizes. You can image and etch this mesh on a regular double sided board, direct plate it and then copper plate. Examine the board every few minutes and see how the gaps in the mesh "close". The rate of closing should give you some idea regarding the time.
Of couse, you must keep in mind that this time dependency that exists on the outerlayer of a board is different from what you get inside a via, especially a small and deep via. For vias you may create a board with differnt hole sizes (many coupons - each containing 4-5 hole sizes) partially routed out, direct plate and electroplate it. Every few minutes lift the board out of the plating bath and break off one coupon (your partial routing should be such that would allow easy breaking off of these coupons, but not too easy that would break off during agitation). Microsection the different coupons and get a better knowledge of the time dependency of copper. It is more difficult and time consuming but a little more accurate (the actual current density will depend on the specific board layout and it will be always different from your test board, by definition).

I'll take this opportunity to wish You and all Technetters a very happy and an even happier and less eventfull New-Year.

Yehuda Weisz


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