not with immersion method... SIR test still win the day (if not years  
or more).
On Jan 3, 2020, at 4:51 PM, David Hillman wrote:

> A shorter time than it takes to conduct an SIR  
> test....................
>
> Dave
>
> On Fri, Jan 3, 2020 at 3:49 PM Douglas Pauls <
> [log in to unmask]> wrote:
>
>> Ya gotta wonder how long it takes to plate up 15 INCHES of gold......
>>
>> *Douglas Pauls *| Principal Materials and Process Engr | Advanced
>> Operations Engineering
>>
>> *COLLINS AEROSPACE*
>>
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>> On Fri, Jan 3, 2020 at 3:45 PM David Hillman <
>> [log in to unmask]> wrote:
>>
>>> Hi Murray - if you can get a true ENIG plating chemistry to put 15
>>> inches of gold thickness on a board, you would never want to use the
>> board
>>> as the gold plating would have severe structure and/or solderability
>>> issues. The IPC-4552 specification contains the industry  
>>> consensus gold
>>> plating thickness range that applies to producing an acceptable and
>>> reliable ENIG plating layer. Any gold plating thickness outside  
>>> of that
>>> range would be questionable at best for quality and reliability  
>>> unless
>> you
>>> are working closely with a plating chemistry supplier who is doing a
>> custom
>>> plating bath composition. One of the early issues of ENIG plating  
>>> was the
>>> industry asking the plating chemistry suppliers to provide an  
>>> immersion
>>> gold plating thickness that exceeded the acceptable physics of the
>> plating
>>> chemistry (basically this is how we discovered "black pad"!).
>>>
>>> Dave Hillman
>>> Collins Aerospace
>>> [log in to unmask]
>>>
>>> On Fri, Jan 3, 2020 at 3:30 PM Campbell, Murray <
>> [log in to unmask]>
>>> wrote:
>>>
>>>> Happy New Year All,
>>>>
>>>> Is there any good reason to call out a maximum gold thickness /  
>>>> nickel
>>>> thickness on fab notes or is it sufficient to rely on simply  
>>>> stating
>> that
>>>> the fabricator shall follow ipc-4552 minimum thickness?  I have  
>>>> seen
>> some
>>>> companies state that a maximum thickness upwards of 15 µin to be
>>>> acceptable.  Is there any value in stating an upper range?
>>>> I know it states in 4552 that an upper range had been debated  
>>>> and not
>>>> necessary but I still see an upper added to fab notes.
>>>>
>>>> Regards,
>>>>
>>>> Murray Campbell
>>>> PCB Design Specialist
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