Mark--
     Comments on your questions based on the way we do designs at my company..
      
 1.) Circuit Routing Programs:
     Our electrical engineers are more concerned with parallelism between
     layers, .008 mils on a layer vs .005 mils between layers, and they
     go out of their way to ensure that clad runs are NOT NOT parallel
     from layer to layer. Does it mean anything-- they think so. ABSOLUTELY
     notify your customer, if you are contemplating modifing ANY SUPPLIED 
     DATA, phototooling or Gerber !!!!! That's a golden rule.

 2.) Plated Hole/Trace Spacing:
     With todays technology and hardware, again in my working enviorement, 
     I don't think the fab tolerances work that way. I beleive that number
     is for all manuf tolerances, but for clad spacing we normally don't 
     see more than + .001/- .003 mil. However, a board fabricator should
     be the one to comment on that question.
 
 3.) Drill/Gerber Data Misregistration:
     I can not comment on this question because we supply only the Gerber 
     data and the board fabricator will extract the drill information, which,
     by definition, equals the gerber locations.
                             Hope this is of some help.
                                         Bob Vanech   [log in to unmask]