Good idea ,but would it be an idea also to check?
 the flux in the core solder may  interfere with your measurement - it maybe you
end up monitoring  the SIR of  the flux used to attach the test wires and not
the condition of the board. Check with your supplier.

Mike Fenner
BSP
--------------------------
   Find two (or more) parallel traces at a known spacing, preferably 10 
     mils and isolate each trace between a solderable land on the other 
     side of the panel and an open end of known length using a sharp knife 
     that does not lift the trace. 
     
     Solder a wire to the component side of the via hole and use the 
     parallel traces as an IPC comb. You will have to count the squares to 
     correlate with an IPC test pattern.

        This method works well for analyzing questionable lots. It is not as 
repeatable as a dedicated panel, since phototools are more precise than a knife.

Aric Parr
[log in to unmask]
______________________________ Reply Separator _________________________________
Subject: SIR Testing
Author:  [log in to unmask] at internet
Date:    12/18/96 4:48 PM


Can anyone tell me if it is acceptable practice to cut a "coupon" from a 
production run board and run it as a SIR test coupon. I know that IPC 
has coupons just for this purpose but in the case I have in mind they 
were not used.
     
Steve Collins
PCB Design Supervisor
TSX Corporation
El Paso, TX
Ph: (800) 351-2345
Fax: (915) 543-4898
email: [log in to unmask]

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