Charles:
Besides the board warpage, the lack of contact between the pins and the pads
after reflow could be also due to a combination of pad size, solder paste volume
(stencil apertures/thickness), component lead coplanarity and lead temperature
reached at reflow (especially for ceramic devices). Bottom line is that during
reflow, the molten solder should have enough height to compensate for the lead
height variation and be able to readily wet all the leads. Hope this helps.
Regards,
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______________________________ Reply Separator _________________________________
Subject: Rule: Pins popping up
Author: Richard Krug at ftl19
Date: 11/13/96 8:32 AM
Technet:
I have a board about 13.5" x 4.5" (PC plug in card), .062" thick,
8 layer, FR4, 1 oz copper, 2 power planes, with 16 100 pin TQFP
packages (0.5mm lead pitch) spread across the board (2 rows of 8), as
well as many other PLCC and SOIC devices.
The problem we are having with these prototypes is that some pins
on the TQFP's pop up durring handling. The boards seem to be too
flexable, which probably causes the pins to break off the pads. Is there
a way to make the board more rigid besides using board stiffiners? In
other words can anything be done as far as changing the board stack up,
or will using thicker copper help this situation? Or are there different
types of FR4 available? Or is there something I am not looking at?
Also, what would be a good pad size for the 100 pin TQFP chip?
Currently I am using 1.2mm x .25mm, but I think the IPC recommends 1.6mm
x .35mm, but it doesn't look like it would allow any soldermask between
pads. Or does anybody even bother with soldermask between pads at .5mm
pitch? What is the middle ground?
Thanks in advance!
Charles Wills
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