Mike, unfortunately my information from the customer is basically what I had
previously reported. They do only measure the number of opens as the defect
rate and they seem to be content with this method, at least for the time
being. I would be interested in your ICT results if you can share them. Thanks.


Dave Rooke - Circo Craft
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______________________________ Reply Separator _________________________________

>     I would be interested in assisting you in your investigation. However  
>     I think to be useful you must define ppm more closely.
>     Ideally the metric must: 
>     1)take into account the complexity/density of interconects per unit 
>     area.
>     2) Define the causes of failure to be included. EG: Misplaced 
>     components should not be counted as having dry's or shorts, but 
>     measured separately.
>     3) Be realistic. You cannot count the exact number of opens/shorts 
>     from failed PCBs at ICT, merely the event and it's cause. A component 
>     with a quantity of shorts or drys on a single IC will inevitably be 
>     recorded as simply Dry IC? or Short IC?
>     
>     I will be happy to provide you with our ICT results.
>     
>     Regards
>     
>     Mike Fugl
>     Snr Prod Eng
>     Psion.
>
>
>______________________________ Reply Separator
_________________________________
>Subject: PWB Solder defect rates
>Author:  [log in to unmask] at INTERNET
>Date:    7/12/95 8:38 AM
>
>
>        I am interested in actual soldering defect rates found "out there".
>While visiting a main customer, I was shocked to hear that the number of 
>open circuits detected at "in-circuit testing" was running around 25 ppm. 
>Apparently this problem is due to insufficient solder during surface mount 
>assembly and is due to many different causes. This value of 25 ppm was 
>stated as "above average" but at the same time was considered "okay" due to 
>the complexity and large number of interconnects on the pcb's. I would like 
>to ask the following questions:
>     
>1)      Can anyone share their actual "solder open" defects rates and 
>provide           how they compare with the industry average? (I would 
>attempt to                 establish the distribution curve of responses and 
>publish later) Can you         include bare board finish (ie HASL, reflow 
>tin-lead, OSP etc...)?
>     
>2)      Is this considered normal???
>     
>3)      Is there a repair procedure recommended by IPC to repair these types 
>of         defects and is there a reference IPC document?
>     
>4)      How are the defect rates normalized based upon assembly complexity, 
>board size and SMD pad geometries?
>     
>5)      Has this defect rate been "self-inflicted" with the advent of 
>no-clean          fluxes and solder paste?
>     
>     
>Thanks
>     
>Dave Rooke - Circo Craft 
>[log in to unmask]     
>     
>
>
>