>We have had some Cmos electronic assemblies delivered to us from a
sub-contractor that were packed in ordinary brown recycled cardboard
inners with no antistatic bag protection. The cardboard inners were in
contact with parts of the circuit. They were delivered by road over long
distance, about 2000 miles. The boards were packed in an antistatic
environment, so the only risk is of static damage due to movement in the
packaging while in transit.
>We would like some opinions on the level of certainty with which any
static damage would be detected by our normal ICT and temperature cycled
soak testing procedures. We are concerned that some devices may have been
degraded without failing totally, causing reliability problems in the
field. Is there any data available which would give us either the
certainty to scrap the boards, or embark on a testing program which would
give us assurance that the boards are not likely to fail after passing
these tests.

I sent this message on to someone I knew has extensive experience in this
area - this was his reply:

FROM: Andrew J. Franklin - QA/Rel/WLR Staff Engineer
Tel Office - 011 44 1475 655323,Tel Home - 011 44 141 357 1240
Office Fax - 011 44 1475 655323,Home Fax - 011 44 141 357 1240
SUBJECT: Latent ESD damage

Hi Dave - We use high voltage stress testing to screen out potential failures.
In this case a burn-in at the max operating voltage for 48hrs could help.
Without full burn-in you are unlikely to detect any wear our issues though, but
this may help with infant mortalities.


Best Regards .... Andy
Internet ID - [log in to unmask]
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