Ed didn't say in his original e-mail if the "padless" connections were on
IL, OL or both.  Happy's comments appear to be limited to OL padless.  Has
there been testing done to see if the same reliability benefit is realized
if padless innerlayer connects are used?
Mike McMaster
RF Product Engineer
Merix Corporation
503-992-4263



> ----------
> From:         Happy Holden[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;[log in to unmask]
> Sent:         Wednesday, September 17, 2003 8:33 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] Reliability question
>
>
> Hi Ed,
> You will probably get a lot of different opinions on this subject based on
> your questions.  And, YES, microvias boards are being designed today with
> landless vias.  Three  pictures of them are attached.  The unique thing
> about landless vias, is that extensive reliability testing  have shown
> them to  BE MORE RELIABLE THAN VIAS WITH LANDS!  But this is mainly in
> Europe, because we have not done a lot of testing on this while the
> Europeans have.
>
> Here is what we found when we tested landless vias nearly a decade ago on
> small and large THs in thick and thin boards.
> In 1988, a large U.S. OEM was working with OKI of Japan.  OKI was shipping
> multilayers with the surface having landless vias.  This did not match
> their standards and IPC Specs, but the Japanese insisted that these were
> reliable.  Not wanting to insult the Japanese, this OEM used their own PC
> Fab facilities to build and test the landless vias as well as vias with
> lands of various annular rings, materials thicknesses, finished hole dia
> and plating thicknesses.
>
> Some  results were predictable and other very surprising:  Small holes,
> thin copper plating  and high aspect ratios all led to early hole
> failures.  But the holes that refused to fail were the landless ones.
> Even when the plating in the landed-small holes were thin, the same dia.
> holes as landless on the test boards had sufficient copper to be reliable
> (this later test showed was a current density thing).
>
> This data was turned over to the PhD Reliability  Scientist to explain.
> Not only did they explain it, they created a modified Coffin-Manson model
> that predicted the early failures of the small annular ring holes.  The
> work was so significant, that the decision was made "on-high" not to
> publish the data and let everybody in on the 'secret'.  Landless vias are
> a significant performance, density and reliability advantage, so why
> inform your competitors about it.  Landless vias have been in production
> on high-density and form-factor driven products at that OEM ever since.
>
> The issue with your boards is that they were not designed or built to be
> 'landless'.  They may be landless now, but it also sounds like they have
> SOME annular ring on the holes due to misregistration.  True 'landless' TH
> of 0.062" material and what sounds like 2 mil of plating per wall should
> be reliable.  BUT, holes with 1, 2 or 3 mil of annular rings are the ones
> the OEM found failed early.  The cause was corner cracking.  As the
> material was thermal cycled, the smaller the annular ring, the higher the
> angle of the land to the barrel, and the earlier it cracked and then
> propagated around the hole until it severed the trace connection.  So your
> boards may be in this case and not one of true "landless".
>
> Thermal cycling is one way to test it if you can afford the time and
> materials.  Maybe a faster way is to use the new HATS testing machines
> that some commercial labs have (Highly Accelerated Thermal Shock).  New
> sample coupons will have to be made but the results look like they predict
> what will happen in service  or by IST testing (at least Delphi thinks
> so).  Their Web site is: www.hats-tester.com  There is technical papers
> there, contacts and coupons.
>
> Not a lot has been published on 'landless' and small annular ring holes.
> Good Luck
>
> Happy Holden
> Westwood Associates
>
>
>
>
> I have a question concerning the reliability of a PCB that has little to
> no
> annular ring on the via holes on the external surfaces of a multilayer
> board:
>
> -there are about 100 such holes on the board
> -all components are through hole
> -the board is four layers, 0.062" thick
> -solder mask fills most of these via holes
> -the pad size is about 0.024", with a hole drill size of 0.020", and
> finished hole size of about 0.016"
> -the trace coming into the hole is 0.008" wide
> -there are a few locations where a trace enters a hole and there is no
> land
> (pad) at the junction of trace/hole, just the width of the trace
> -the specification is for 2 ounce copper finished amount
>
> The board house has 100% electrically tested the boards for shorts and
> opens
> and found no failures, and believes that the boards will be reliable. We
> have assembled, wave soldered and tested (before discovery of the problem)
> about 30 of the units and have found no failures related to this issue.
>
> The boards do not meet IPC-A-600 specifications. The customer designed the
> board and did not call out any IPC spec.
>
> My concern is the long term reliability of the trace to hole junction. It
> seems that I remember hearing of high density boards actually being
> designed
> without pads: the traces came directly into the hole. Has that been done
> successfully?
>
> Is the reliability questionable? Will successful thermal cycling of the
> assemblies indicate long term reliability? Any thoughts or suggestions
> will
> be appreciated.
>
> Thank you,
>
> Ed Berti ---------------------------------------------------
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