Hi Sherif.. my two cents...

> 1) Is it correct that bare boards electrical testers may not detect opens
caused by complete copper cracks (circomfrential) inside via holes because
the pressure from the test pins do close the crack? ( I personally do not
think so. The copper crack width measured from the cross section is
0.0004"). The boards I'm talking about are Immersion Silver plated.

This is possible but an alert test operator should become aware very quickly
that something is wrong. This condition (almost??) never affects one via
only so a few of the affected vias will read open and should be analyzed
before accepting the boards which passed.

A related question: Are these testvias or stitchvias ? If these are
testvias, there may not be a testpin on the "end of net" side

>
> 2) How about via copper cracks if the boards are HASLed. Would the
Tin/lead inside the via holes allow enough conductivity to "hide" the copper
crack?

Yes

> 3) If the copper plating thickness inside the hole is considerably reduced
(for example, down to 0.0004" from 0.001") would that be detected by the
E-tester as high resistance?

No, the change in resistance is in the micro ohm range. Electrical testers
are by far not sensitive enough to detect this.

 4) How the test parameters affect the above issues?

Not at all (IMHO)

good weekend

Wolfgang

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