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May 1999

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Subject:
From:
"Robert D. Green" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Mon, 24 May 1999 16:12:51 -0400
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text/plain (142 lines)
     
  Hey!  A question in my field for a change!  
  
  Bob, the folks are correct about JTAG/BoundaryScan.  For this testing 
  technology to be even applicable, the designers must utilize components with 
  BoundaryScan capability in them, and then connect them in a certain fashion.  
  Typically you will only see this utilized on boards with large, active 
  components. 
  
  
  As for "Board Level Testability Analysis" this is another way of saying 
  "Design for Testability" (DFT).   
  
  DFT includes:
  
  - Mechanical considerations
    (ex: test pad sizing/spacing, tooling pin sizing/clearances)
  - Electrical considerations
    (ex: control line availability for ICT Testers, BIST control)
  
  This stuff revolves around two arenas, 1) the ability for In-Circuit testers 
  to make connection to the assembly (fixturing) and manipulate it (circuit 
  design), and 2) how well the assembly is designed to be tested in a 
  functional fashion (functional test, diagnostics, Built in Self Test, etc.)
  
  Typically your Test Engineer (or outside test house) should be compiling a 
  set of DFT guidelines based on their test capabilities.
  
  Unless I've been asleep or blind (both entirely possible) most of the folks 
  setting up guidelines for design (IPC, SMTA, etc.) don't have much to say on 
  the subject of DFT although I would love to be proven wrong.  The result is 
  alot of us have developed our own DFT Guidelines in self defense.
  
  Now that your head is spinning, send me an e-mail directly with a bit more 
  info on your role in this and what you make, and I can elucidate you to death 
  on this subject!  <lol>
  
  -------------------------------------------------------------
  Robert D. Green - Supervisor, Test Engineering
  Hadco - Value Added Manufacturing
  e-mail [log in to unmask]
  
     


______________________________ Reply Separator _________________________________
Subject: Re: [TN] JTAG.??
Author:  "Stephen R. Gregory" <[log in to unmask]> at smtplink-hadco
Date:    5/24/99 2:18 PM


In a message dated 5/24/99 10:56:13 AM Pacific Daylight Time, 
[log in to unmask] writes:
     
<<  To all...
     
   I attemted to send this out Fri., but I don't 
   think it went. I'll try again. My boss asked me
   if I knew anything about a "Board level testability 
   analysis including the role of and use of JTAG"? I 
   responded with an very educational DUH!!! Help, 
   does anyone know what this is about??? Any help 
   would be appreciated and thanks in advance.
     
   Regards,
   Bob Vanech
   Mango Computers
   (203) 857-4008 x108 >>
     
Hi Bob!
     
JTAG is a sorta kinda trade name that came about from a joint effort by 
certain companies, that's really talking about Boundry-scan testing. If you 
go to:   http://www.corelis.com/products/scanovrv.html  there will be a real 
good overview about Boundry-scan testing and what has to happen as far as 
design and whatnot in order to able to accomplish it. Below I've pasted a 
couple of paragraphs from that page that gives a general description about 
it...
     
-Steve Gregory- 
     
Boundary-Scan Standard Background 
     
Boundary-scan, as defined by the IEEE-1149.1 standard, is an integrated 
method for testing interconnects on printed circuit boards that is 
implemented at the IC level. The inability to test highly complex and dense 
printed circuit boards using traditional in-circuit testers and bed of nail 
fixtures became evident in the mid eighties. Due to physical space 
constraints, fixturing cost increased dramatically while fixture reliability 
decreased at the same time. This problem has been further complicated by the 
growing use of complex custom application specific IC's (ASIC's) that require 
extensive test pattern sets. This not only increases test development cost, 
it also increases test times and decreases test coverage. 
     
In 1985, companies such as  IBM, AT&T, Texas Instruments, Philips Electronics 
NV, Siemens, Alcatel, and Ericsson, recognizing the need for a uniform 
solution to these problems, took the initiative to overcome these issues and 
founded the Joint Test Action Group (JTAG). This initiative quickly led to a 
new boundary-scan testing (BST) method, adopted by the IEEE as Standard 
1149.1 in 1990. Since that time, this standard has been adopted by major 
electronics companies all over the world. Applications are found in high 
volume, high-end consumer products, telecommunication products, defense 
systems, computers, peripherals, and avionics. Now, due to its economic 
advantages, smaller companies are starting to take advantage of BST. 
     
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