Hello Technetters:

I have some questions for the contract and OEM manufacturers.
	
Have you experienced any problems with multilayer PWBs that do not utilize
thermal relief for power connections on the stringer (break-out) vias for
surface mount components?  This can include chip caps and resistors, BGAs
and QFPs.  Ex:  Power connections using 0.02 to 0.03 inch trace widths on
discrete components, 0.008 to 0.011 inch trace widths on QFPs, and 0.005 to
0.006 inch trace widths on BGAs.  All connections direct to plane.  All
signal layers ½ oz, plane layers 1oz base material.

What size test point pads are you requesting/requiring for ICT?  What is the
desired/minimum pitch between these test points?  What type of tip do you
have the most success with?

Are you having better luck mounting BGAs on PWBs that were constructed with
a high Tg FR4 verses standard FR4 material?  Do you still see HASL as the
predominant finish on PWBs with BGA or QFP devices?  

Polarity orientation and component proximity errors notwithstanding, what
are the most common problems associated with assembly that can be traced
back to a poor layout?  What seems to be your most consistent problems
associated with a given layout?

Do you mostly rely on an assembly drawing or the silkscreen marking to
place, inspect, and troubleshoot polarized components?  If a PWBs component
density is such that some of the reference designators and part outlines
have to be removed for clarity is it advantageous to have a single dot of
ink in the center of the component pads?  To whom and what kind of advantage
would this afford?  Could this ink dot height be of concern for chip-type
parts in that both terminals do not contact the pads?

I hope this post was not too long winded.  I still have additional questions
that I would like answers for, but will save those for another time.  Thank
you for finding time out of your busy schedules to answer these questions.  

Best regards,
Ewart Speer


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