There is much written, but seemingly little consensus, on SIR Test 
     methods.  I'm using IPC-TM-650, number 2.6.3, as a reference.  Any 
     insight that can be provided regarding the following open issues, 
     in the context of IPC Level 2 testing of printed circuit card 
     assemblies, would be appreciated.
     
     1) Bias voltage level, nominal set to -48vDC, but some argue in favor 
     of lowering the voltage closer to operating level, i.e. -5 or -15vDC?
     
     2) Effect of REVERSING the voltage polarity when going from the BIAS 
     to the TEST sequence, e.g. if bias is -48vDC, going to 100vDC for 
     measurements?
     
     3) Appropriateness of the "ohms/square" conversion principle in 
     establishing insulation resistance thresholds for non-standard 
     patterns, e.g. inter-leafed footprints?
     
     4) Pass/Fail criteria:
     
        a) Absolute threshold per IPC (100Mohm) or Bellcore (3Gohm) even    
           with non-standard patterns
     
        b) Scaled threshold per "ohms/square" concept
     
        c) Two decade drop in insulation resistance anytime during test
     
     
     Thanks very much.
     
     Steven Beckman
     Lockheed-Martin Commercial Electronics
     603-885-2550 
     
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