Bob Willis writes:

Does any one have any experience in wave soldering TSOP devices. What process
parameters have been examined and what failure modes have been seen?

Bob Willis
Tel:  (44) 01245 351502
Fax: (44) 01245 496123




Allen-Bradley component engineering studied wave soldering surface mount technology integrated circuits and found the risks to be high.

The following is from Allen-Bradley Component Engineering Paper  CE#2638   CER#9400588

Test results

-Acoustic Imaging Scans of devices processed thru wave solder show die and lead frame delamination.  Cross-sectional analysys indicated micro-cracks from the lead fingers to the die paddle.  Delamination failures can produce intermittent device operation.  Micro-cracks can cause internal contamination and metal migration failures.

-Permanent parametric shifts of critical elecrical characteristics were recorded after exposure to wave solder temperatures.

Supplier response

-Suppliers do not perform standardized tests on IC component qualification for wave solder attachment.  Wave solder compatability tests are not generally performed for package qualification or package re-qualification after a design or material change.

-Only 20% of suppliers contacted provided test data relavent to wave solder.  Most suppliers indicated that wave solder tests had not been performed.

-Wave soldering of SMT IC's is not an industry standard practice and was not considered when IC Package Technology was originally developed.

Commercial issues

-Similar type devices are not manufactured identically.  Alternate sources for logic, linear and memory devices becomes difficult if not impossible, and severly restricts purchasing options when parts are placed on allocation.

-There is no guarantee that a supplier will not change materials or processes which may invalidate in-house qualification tests.



If you want to pursue the tsop issue.

Per CE#9400823

1.  Copper leaded Tsops have acceptable solder joint life.  Few suppliers offer this.

2.  Alloy-42 leaded Tsops are acceptable under the following conditions:

A.) The substrate CTE is less than 14 ppm/deg C and limited to 4layers.  A CTE requirement of 14-16ppm/deg C must be on the pcb drawing.

B.) The max repeated upper temp cycle limit (at the device) is less than 50 deg C.

C.) The Tsops are encapsulated.

D.) Special compliant alloy-42 leads are used. (currently not available)


I am not in Component Engineering.  I can only pass along what I have read.......and this is it.

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John Laur
Rockwell Automation
Allen-Bradley Co Inc.                 

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