Hello Steve and Phil,
Steve, I'm not sure if this answers your question, but it's a issue I
believe needs to be addressed.  The process of filling vias with LPI
is done in almost every board shop in the US.  When no via fill is
required, there is no relief above the holes (on the artwork) and the
mask in the holes is exposed  and doesn't develop out.  This creates
some holes that are filled with mask (using screen printing) and some
that are not.
My biggst issue is with the ones that are filled (or partially
filled).  The screen printed mask has solvents of > 30% by volume.
The tack dry process is optimize to remove most of the solvent for
coatings of 3.0 to 0.5 mils in thickness.  It is not uncommon to have
20-30 mils of mask in a plugged hole.  The solvent is not removed
during any of the next process steps including final cure.  Thus the
material in the hole can and does expand during thermal processes
and create volcano's that release contaminates.
One option to is to always create a dot pattern on the film. This
will block the exposing of this material and at least eliminate the
plugging of the via with uncured material.  If some mask is left in
the hole after developing it will not create any future process
problems involving solvent entrapment.
Via plugging should be done before mask coating using a 100%
solids material and from one side only.   Once completed, the
mask process simply coats the cured plug.
Joe Dickson
Tyco Santa Clara


> Date:          Tue, 17 Aug 1999 09:17:35 -0700
> Reply-to:      "TechNet E-Mail Forum." <[log in to unmask]>,
>                Phil Crepeau <[log in to unmask]>
> From:          Phil Crepeau <[log in to unmask]>
> Subject:       Re: [TN] Via hole fill...
> X-To:          [log in to unmask]
> To:            [log in to unmask]

> hi,
>
> paragraph 9.2.5, sentence 2 states, "plated through-holes not exposed to
> solder because of permanent or temporary maskants and used for interfacial
> connections need *not* be filled with solder."
>
> case closed.  sounds like a non-value added problem.
>
> phil
>
> -----Original Message-----
> From: Stephen R. Gregory [mailto:[log in to unmask]]
> Sent: Tuesday, August 17, 1999 7:59 AM
> To: [log in to unmask]
> Subject: [TN] Via hole fill...
>
>
> Hi all !!
>
> I just got into a little debate about via fill. Say for instance you get
> some
> boards in at recieving where upon inspection, you see via's that have mask
> partially in the holes. The via's were not intended to be tented, but on the
> same hand the artwork was never relieved to prevent the vias from being
> covered with mask. The vias are open, but do have mask partially down inside
> them as it appears the mask used was a LPI that doesn't completely tent vias
> well.
>
> I was asked if this was a problem, I said no...unless the board was going to
> go to ICT where vacuum was going to be needed, or maybe good via fill was
> needed to have good probe contact. But since the mask was not relieved, it's
> not a problem...I interpret that as the via's were never meant to be filled.
> I was then asked will some of them fill? I said maybe some will, but
> probably
> most won't. Then I was told that according to 9.2.5 (page 17) in the
> J-STD-001B the vias HAD to meet Figure 9-2 (on page 18) of at least 75%
> fill.
> I said not all...the via's were never intended to be filled, whether they
> fill or not is not a problem at all. It won't affect reliability or function
> if they do, or do not fill. I was told I was wrong....am I?
>
> Thanks!
>
> -Steve Gregory-
>
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