hi,

paragraph 9.2.5, sentence 2 states, "plated through-holes not exposed to
solder because of permanent or temporary maskants and used for interfacial
connections need *not* be filled with solder."

case closed.  sounds like a non-value added problem.

phil

-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, August 17, 1999 7:59 AM
To: [log in to unmask]
Subject: [TN] Via hole fill...


Hi all !!

I just got into a little debate about via fill. Say for instance you get
some
boards in at recieving where upon inspection, you see via's that have mask
partially in the holes. The via's were not intended to be tented, but on the
same hand the artwork was never relieved to prevent the vias from being
covered with mask. The vias are open, but do have mask partially down inside
them as it appears the mask used was a LPI that doesn't completely tent vias
well.

I was asked if this was a problem, I said no...unless the board was going to
go to ICT where vacuum was going to be needed, or maybe good via fill was
needed to have good probe contact. But since the mask was not relieved, it's
not a problem...I interpret that as the via's were never meant to be filled.
I was then asked will some of them fill? I said maybe some will, but
probably
most won't. Then I was told that according to 9.2.5 (page 17) in the
J-STD-001B the vias HAD to meet Figure 9-2 (on page 18) of at least 75%
fill.
I said not all...the via's were never intended to be filled, whether they
fill or not is not a problem at all. It won't affect reliability or function
if they do, or do not fill. I was told I was wrong....am I?

Thanks!

-Steve Gregory-

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