Mark, I'll try to throw some light on hole-fill requirements without
actually answering your question(s).  Here goes:
- Some (long) time ago a fellow at IBM (Roger Wild) did some fairly
comprehensive studies of the reliability of pth's during thermal cycling as
a function of hole-fill.  His data showed that the most reliable condition
was for a hole to contain NO solder.  The next most reliable condition was
for the hole to be 100% solder filled.  
- The DOD folks were at that time involved with an industry working group
and together they were driving the specification/standards train.  DOD had
previously experienced problems with pth failure (open circuit) at the knee
of the pth due to z-axis Tce.  Roger's data suggested that holes which had
experienced complete solder fill (with solder flowing out over the topside
knee) were fairly reliable (solder reenforced the weak knee).  Consequently
the DOD folks required the solder to fill the hole, but allowed 25%
recession.  They were careful to choose the word "recession" because that
implied that the solder had filled the hole completely, and then receded as
it came off of the wave (as contrasted to the present allowance for
"depression", a term which does not imply that the hole was filled enough to
support the knee). 
- To my knowledge there are no contemporary definitive studies which relate
hole fill to reliability.  
- The requirements in ANSI/J-STD-001B are identical to those of IPC-A-610B
which you mentioned EXCEPT there is no exclusion for Class 2 as defined by
Figure 4-2 of 610B.   
- You say you have an 8 layer pwb with multiple ground planes and have
difficulty achieving 100% hole fill, then inquire whether a hand soldering
touch-up would effect long term reliability?  My GUESS would be that: 1) if
your end-item does not experience temperature variations greater than +/-
25F from nominal during operation, and if you are achieving 50% or more hole
fill during wave soldering, that you would probably not gain anything by
touching up (filling) the pth's;  2) however, if the end-item experiences
temperature variations greater than +/- 25F (from nominal) during operation,
and if the hole fill is less than 50%, then I would probably touch-up (fill)
the pth's with solder.  Either of those Guesses are dependent on other
factors which include: pwb laminate type & grade (e.g. Z-axis Tce), presence
of vibration and/or mechanical shock, probability of thermal shock, etc.,
etc.  Needless to say the best option is to manipulate the process (preheat,
flux activiy, component solderability, transport speed, etc.) to achieve
maximum hole fill.  
Hope my two-cents worth has not muddied the waters excessively. 
 Regards, Jim Moffitt/EMPF
    
At 01:26 PM 11/20/96 +0000, you wrote:
>
>G'day Technetters-
>
>I'd like to 'springboard' from what Mark Weiler wrote, way back on
>Thursday, October 10, 1996  :
>
>>     We are building a board that has 8 layers with multiple ground 
>planes...
>>     making it difficult to optimize the wave solder profile to get 100% 
>fill...
>>     ... on the top side of the board.
>>
>>    The IPC A-610 rev B specification calls out 75% fill as being 
>acceptable
>>    (table 4-1, pg. 52) on through hole solder joints....
>>
>>    Is a solder joint that is 75% filled over the wave stronger (more 
>reliable)
>>    than a solder joint that has been touched up to get to 100% with a 
>fillet?
>>
>>     What is the effect to long term reliability of touching up a through 
>hole
>>     solder joint?
>>
>>     I would really like some reference material on this subject if anyone 
>has
>>     a  source.
>>
>>     Thanks,
>>
>>     Mark Weiler
>>    [log in to unmask]
>>     512-728-8323
>>******************
>
>The questions raised have been bugging me for a while, too.  And some
>from a slightly different perspective, as well...
>
>IPC-A-610B, Table 4-1 calls out 75% fill as the minimum acceptable condition 
>
>for class 3 assemblies.   If Class 2, however, would it be appropriate to 
>apply
>the exception of Fig. 4-2, when internal conductive layers are involved?
>Or is it incorrect to assess any of the internal layers as corresponding to 
>the
>heatsink plane unless one of those layers is specifically called out as 
>such?
>
>At some point, it seems, the internal (non-"heatsink") layers will introduce 
>
>the cumulative effects comparable to those introduced by a heatsink plane.
>Is it expected that solder process modifications can and should be varied
>to accomodate any number of current carrying layers and still accomplish
>the required fill?
>
>Is "fill" is merely a visual indicator of the wetting success and the 
>integrity of
>the PTH, or is there something less obvious to this requirement?
>
>Or am I missing something...like *the point entirely* ?
>
>Thanks for any and all help!  (And, Mark - thanks for the boost.)
>
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