Hey doctor Bill,

Appreciate the input. I was headed down a similar path with regard to most
of your stuff, especially the coplanarity issues. For our new components, I
still do not have a data sheet or drawings indicating column wire length,
exactly (probably .070") and tolerances (hope there very tight?).

Hadn't thought much about anything but eutectic and I sure agree with you on
no clean based on experience gained with "lesser" CGA's.

Probably going gold, though OCC is being considered and I think that is the
path to follow as well.

I appreciate the advice concerning ball size in paste as well as MOTS. I
look very closely at this as it didn't seem to have much affect on 1mm stuff
and over but did affect some .5mm CSP's I did last year.

I'm concerned about pnp placement accuracy as well as rework placement
requirements using the SRT. I'm also concerned about using whatever type
paste application technique for rework (no kidding). Micro stencils worked
ok for "lesser" device types on .8 stuff, but 3000 I/O's is another story.
Any thoughts here?

I think we can extrapolate the thermal profiles from past experience but the
current test board design is over 30 layers now and I can't even tell you
how large the panel but looks to exceed "standard" 18 x 24" size used on
some other product.

I too will keep you posted as we get closer to proving the initial design
within a week or so.

Thanks so much Doc and I love your new line of reading glasses,

MoonMan