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February 2001

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Sender:
TechNet <[log in to unmask]>
X-To:
Steve Telgen <[log in to unmask]>
Date:
Wed, 21 Feb 2001 08:16:18 -0800
Reply-To:
"TechNet E-Mail Forum." <[log in to unmask]>, John Parsons <[log in to unmask]>
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Subject:
Re: FAB - Reality Check, Tooling Holes and Profiling
From:
John Parsons <[log in to unmask]>
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<001201c09c13$91bbf5a0$4200a8c0@stelgen>
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Circuit Graphics Ltd.
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Steve,

And with pinless routs you are having no problems maintaining the
+/- 0.005" tolerances seen on many of todays fab drawings?  Or do
you not see tolerances spec'd this tight?

Regards
John Parsons

> John, we use pinless routing with '80s vintage Excellon Mark IV's.  A lot of
> today's designs don't leave a lot of room for additional tooling, and
> pinless saves on set-ups.

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