Hi Dave. I would suggest you read IPC-2221  Generic Standard on Printed
Board Design. In section 6 it gets into Electrical Conductor Spacing. I know
this is not what you are looking for, but you need to start with the design.
The second piece of the equation is the proximity of each component to each
other. Space must be provided to allow the tooling accessibility for the
removal and replacement of the component if necessary. Now to the shorting
issue. To me this is paste related. There are some IPC test panels described
in J-STD-005 relative to pad spacing and this is used to measure slump of
the solder paste. In other words how much will it slump during the soldering
process and will this slump create shorts to adjacent pads and leads. The
last issue is solder mask coverage between conductor traces. Check the value
of having the via left uncovered and perhaps it can be covered to prevent
the problem all together.

Hope this helps.

Regards,
Leo Lambert EPTAC Corp, Amherst NH, 1-800-643-7822
  -----Original Message-----
  From: TechNet [mailto:[log in to unmask]]On Behalf Of Dave Chapman
  Sent: Tuesday, October 08, 2002 2:28 PM
  To: [log in to unmask]
  Subject: Re: [TN] component spacing


  What is the minimum spacing between a via and an active SMT pad to avoid
shorting. I am looking in IPC 610 but I do not find dimensions only
conditions to avoid.
  Dave Chapman
  Manufacturing Engineer
  Circuit Service Inc.

    -----Original Message-----

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