Char, I'll attempt to answer these questions as briefly as possible,
however, there are many additional small details that are not easily
addressed via E-mail. 

Here goes:


>     Technetters,
>     
>     Hopefully someone could help me answer these 2 questions on a report 
>     I'm writing.
>     
>     
>     1.) HOW DOES THE VENDOR COMPENSTATE FOR PLATING IN HOLES WHEN THE 
>     DESIGN IS UNBALANCED. DESCRIBE THE CONSIDERATIONS IN A DESIGN TO 
>     ACCOMMOATE THIS SITUATION.

Pwb manufacturers strive to work closely with their customers' designs in
order to avoid these types of problems. In this fashion the problem never
occurs. However, in cases where it is impractical due to cost of redesign,
the board manufacturers would have no other choice than to drill these
isolated holes larger than 'typical' in order to compensate for the
overplating that will inevitably occur. This causes complications if, as in
the case of multilayer manufacturing, inner layer pad sizes are already
fixed. The resulting need for larger holes could result in hole breakout of
the inner layers. Another consideration is the overplating that can result
on the SURFACE of the circuits. This, if excessive, may result in poor
circuitry definition, solder mask thickness issues and perhaps even short
circuits depending on the density.

  HOW CAN A DESIGNER COMPENSATE FOR THIS? 

The best approach would be to ensure that the design rules used for ALL
circuitry layers ENFORCE well balanced circuitry in order to PREVENT the
problem in the first place. (in roughly practical terms this means that the
copper density across each layer should not vary by more than 10%) If the
above cited problem was to exist, the designer could 'help' by increasing
the inner and outer layer pad sizes and maximizing the circuit spacing
between all adjascent circuits. The most blatant violation of this would be
a board that has solid ground plane on half with 2 or 3 circuits extending
to the other half of the board with no other circuitry or copper. Of course
these circuits would be 5/5.


>     DESCRIBE "INTERNAL PLATING THIEF'S", HOW AND WHEN THEY ARE USED.

I believe what you are talking about relates to adding non functional copper
features to maintain this imaginary 10% maximum variation across the board
surface. They should be used in cases where this '10% rule' is violated.
>     
>     2. )DEFINE PROGRAMMING PROCEDURE FOR ELECTRICAL TEST.  

Basically, most high volume ET systems utilize CAD reference which is
basically a netlist derived from the from-to list for all circuits defined
by the designer. During testing, each terminal node of each signal is tested
in order to confirm intentional connections (ie no open circuits) and
confirm that no UNintentional connections exist (ie no shorts).

DEFINE THE AOI PROCEDURE: (AUTOMATED OPTICAL INSPECTION)

Within the last year, a similar CAD reference exists for AOI however, the
database is the GERBER data and NOT the electrical netlist reference.
Basically AOI "pixilizes" (sorry for the poetic license but I just couldn't
resist) the scanned circuit and compares the resulting bitmap against the
bitmap of the CAD reference. In systems where CAD reference does not exist,
the compared bitmap is that of a learned image of a (hopefully) known good
board. All systems also use generic design rules such as track width,
spacing, near opens etc. to detect defects that may not result in
electrically detectable non-conformances.



I hope that this brief description is sufficient.

regards,

Dave Rooke
Circo Craft - Pointe Claire

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