TECHNET Archives

1996

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Bill Dieffenbacher <[log in to unmask]>
Date:
Mon, 02 Dec 1996 16:03:09 -0600
Content-Type:
text/plain
Parts/Attachments:
text/plain (95 lines)
George,

We have had good results with blind vias in SMT pads.  Generally we cannot
even see the via in the pad, but occasionally we see a small dimple which
may show a little underfill of the resin in the blind via as you have
depicted.  This has never presented itself as a problem during assembly.
The surface plating is performed at the same time that other through holes
are plated which means that the resin in the hole, at 'A' in your graphic,
has been roughened up a little due to desmear or etchback processing of
through holes prior to electroless copper.  Also the amount of electroplate
copper on the surface may be sufficient in our designs to prevent any
peeling even if the electoless had poor adhesion to the resin.

Bill Dieffenbacher



At 11:08 AM 12/2/96 -0500, you wrote:
:Hello all,
:
:I have a question on blind via which fill / partially fill with prepreg 
:resin during lamination.  Assume an 8 layer board, blind via 1-6, SMOBC, 
: .062",  standard in other ways....
:
:ASCII Graphic
: _______       _______  Copper Layer 1
: xxxxxx|___A___|xxxxxx  A = Copper Layer 1 in partially filled via hole 
: xxxxxx|xxxxxxx|xxxxxx
: FR-4  | resin |FR-4     FR-4 "x" and plated via hole wall "|"
: xxxxxx| blind |xxxxxx
: -------x via x-------  Copper layer 6
: xxxxxxxxxxxxxxxxxxxxx
:----------------------  Copper layer 8
:
:In area "A", above, the resin fill does not go the the surface of the 
:board.  This is a partially filled blind via, and is an acceptable 
:condition.  However.... The surface of "A" is plated with electroless 
:and pattern plated.  The electroless/plated copper has very poor 
:adhesion on the resin in the hole, and peels off in various subsuquent 
:processes, especially solder coat.  I understand that the "fill" resin 
:surface is very smooth which causes the adhesion failure.
:
:It is my assumption that this is a typical condition for "unfilled" 
:vias.  Is this a vaild assumption?
:
:Are there any situations when this condition poses is a problem?
:
:Do others allow partially filled vias?  IPC-RB-276 accepts a 60% fill 
:for buried vias, but silent on blind vias.
:
:I know that others are trying to use this filled via construction as a 
:surface mount pad (God help you), what experiences do you have with 
:partially filled vias?  
:
:
:
:Thanks for the responces.
:
:
:
:-- 
:
:
:George Franck Jr
:Raytheon E-Systems
:Product Assurance Engineer
:Falls Church Va
:
:***************************************************************************
:* TechNet mail list is provided as a service by IPC using SmartList v3.05 *
:***************************************************************************
:* To unsubscribe from this list at any time, send a message to:           *
:* [log in to unmask] with <subject: unsubscribe> and no text.        *
:***************************************************************************
:
:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Bill Dieffenbacher		   Tel. (607)770-2961
Lockheed Martin Control Systems	   Fax. (607)770-2056
600 Main St.  Room R52F            email [log in to unmask]
Johnson City, NY  13790
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

***************************************************************************
* TechNet mail list is provided as a service by IPC using SmartList v3.05 *
***************************************************************************
* To unsubscribe from this list at any time, send a message to:           *
* [log in to unmask] with <subject: unsubscribe> and no text.        *
***************************************************************************
* If you are having a problem with the IPC TechNet forum please contact   *
* Dmitriy Sklyar at 847-509-9700 ext. 311 or email at [log in to unmask]      *
***************************************************************************



ATOM RSS1 RSS2