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May 1999

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Subject:
vias as test points???
From:
Raymond Klein <[log in to unmask]>
Reply To:
"TechNet E-Mail Forum." <[log in to unmask]>, Raymond Klein" <[log in to unmask]>
Date:
Tue, 18 May 1999 17:10:35 -0700
Content-Type:
text/plain
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text/plain (46 lines) 
Guys,

We are laying out a board for ICT and need to provide .030 inch dia. test
points on a .050 inch grid. The assembly/test shop is willing to accept a
.012 inch hole (somewhere) in the middle of the test point. Unfortunately
this board has a wave solder pass. My questions are:

1. Will flux get trapped underneath the solder mask over the via on the
board top (tented)? Is trapped flux a problem (the assemble uses organic
acidic flux)? short term?  long term?

2. If we un-mask the via on the top will I get solder balls popping through
the via holes?

3. Some of the vias are under SMT parts such as 56TSSOP that have very
little clearance above the board. Will the flux that gets through the
un-masked vias be adequately washed away in the water jet cleaning cycle?

Any advice in this matter is appreciated. Thank you in advance for benefit
of your experiences.

Ray Klein    [log in to unmask]

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