Your construction is a very un-ussual one, because of the panel
thickness and deep blind via. Basically you have at least .045" hole to
be filled with prepeg. This is very difficult to achieve, because:

1. Using prepeg with a lot content of resin (1080), will fill somehow
the hole, but you will have bad registration and unbalanced
construction. One way to resolve this is to use your standard
construction prepeg, but with a higher resin content (current suppliers
are offering prepeg in a medium, smaller and high content resin). Your
results will improve somehow, but not a lot.

2. I think that the customer will not accept a board with partially
filled holes. Most of the time the holes are overfilled, and you need a
light deburring associated with a desmear process, to remove the excess.
Your case is totally different, and I do not have a solution.

3. Your "poor adhesion on the resin in the hole" might be also related
to the drilling process. Burs created by un-optimized drill process will
create point of stress, which will affect the rest of the processes.
This can be avoided by crossection evaluation, right after drill and
correction in drill (backup, entry, drill parameters, drill bit, etc).

Only my $.02.
Julian Mart / [log in to unmask]

PS: I still do have a question: How do you protect the stainless steel
separator from getting in contact with the prepeg?
Thanks


George Franck Jr wrote:
> 
> Hello all,
> 
> I have a question on blind via which fill / partially fill with prepreg
> resin during lamination.  Assume an 8 layer board, blind via 1-6, SMOBC,
>  .062",  standard in other ways....
> 
> ASCII Graphic
>  _______       _______  Copper Layer 1
>  xxxxxx|___A___|xxxxxx  A = Copper Layer 1 in partially filled via hole
>  xxxxxx|xxxxxxx|xxxxxx
>  FR-4  | resin |FR-4     FR-4 "x" and plated via hole wall "|"
>  xxxxxx| blind |xxxxxx
>  -------x via x-------  Copper layer 6
>  xxxxxxxxxxxxxxxxxxxxx
> ----------------------  Copper layer 8
> 
> In area "A", above, the resin fill does not go the the surface of the
> board.  This is a partially filled blind via, and is an acceptable
> condition.  However.... The surface of "A" is plated with electroless
> and pattern plated.  The electroless/plated copper has very poor
> adhesion on the resin in the hole, and peels off in various subsuquent
> processes, especially solder coat.  I understand that the "fill" resin
> surface is very smooth which causes the adhesion failure.
> 
> It is my assumption that this is a typical condition for "unfilled"
> vias.  Is this a vaild assumption?
> 
> Are there any situations when this condition poses is a problem?
> 
> Do others allow partially filled vias?  IPC-RB-276 accepts a 60% fill
> for buried vias, but silent on blind vias.
> 
> I know that others are trying to use this filled via construction as a
> surface mount pad (God help you), what experiences do you have with
> partially filled vias?
> 
> Thanks for the responces.
> 
> --
> 
> George Franck Jr
> Raytheon E-Systems
> Product Assurance Engineer
> Falls Church Va
> 
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