We run traces between SMT pads all the time...so long as there is adequate
room to completely cover the trace with a tough LPI soldermask.  One has to
consider registration tolerances when determining whether the room is adequate.
The LPI must also coat the corners of the trace well (it is always thinnest 
there).  Dendritic growth is the concern when you have bare traces/pads close 
together and operate in a humid environment.

----- Begin Included Message -----

Are there any reasons not to route traces in between pads 
of SOIC or PLCC devices?

Specifically, 8 mil traces between SOIC or PLCC devices 
with 25 mil wide pads.

Thanks for your help

Mark Bartlett
Harmon Industries
[log in to unmask]

----- End Included Message -----

Gary P.
---
                                  Gary D. Peterson
    _/_/_/   _/    _/  _/        SANDIA NATIONAL LABORATORIES     _/_/_/
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