We run traces between SMT pads all the time...so long as there is adequate room to completely cover the trace with a tough LPI soldermask. One has to consider registration tolerances when determining whether the room is adequate. The LPI must also coat the corners of the trace well (it is always thinnest there). Dendritic growth is the concern when you have bare traces/pads close together and operate in a humid environment. ----- Begin Included Message ----- Are there any reasons not to route traces in between pads of SOIC or PLCC devices? Specifically, 8 mil traces between SOIC or PLCC devices with 25 mil wide pads. Thanks for your help Mark Bartlett Harmon Industries [log in to unmask] ----- End Included Message ----- Gary P. --- Gary D. Peterson _/_/_/ _/ _/ _/ SANDIA NATIONAL LABORATORIES _/_/_/ _/ _/_/ _/ _/ P.O. Box 5800, M/S 0503 _/_/ _/_/_/ _/ _/ _/ _/ Albuquerque, NM 87185-0503 _/_/_/_/_/_/ _/ _/ _/_/ _/ Phone: (505)844-6980 _/ _/_/ _/ _/_/_/ _/ _/ _/_/_/_/ FAX: (505)844-2925 _/ _/_/ _/ E-Mail: [log in to unmask] _/_/_/ *************************************************************************** * TechNet mail list is provided as a service by IPC using SmartList v3.05 * *************************************************************************** * To unsubscribe from this list at any time, send a message to: * * [log in to unmask] with <subject: unsubscribe> and no text. * ***************************************************************************