For organic chip carriers where the chip will be wire bonded to the
laminate, requirements for wire bond pad topography tend to be very
strict - nice and flat with no nodules, pits, or other imperfections.
Is a planarization step normally required? If so, how is it done?
We don't do much acid copper pattern plate - can that be plated level
enough to wire bond on without subsequent smoothing/planarizing?
Jonathan Whitcomb
IBM Endicott
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