For organic chip carriers where the chip will be wire bonded to the
laminate, requirements for wire bond pad topography tend to be very
strict - nice and flat with no nodules, pits, or other imperfections.
Is a planarization step normally required?  If so, how is it done?
We don't do much acid copper pattern plate - can that be plated level
enough to wire bond on without subsequent smoothing/planarizing?


Jonathan Whitcomb
IBM Endicott

***************************************************************************
* TechNet mail list is provided as a service by IPC using SmartList v3.05 *
***************************************************************************
* To subscribe/unsubscribe send a message <to: [log in to unmask]>   *
* with <subject: subscribe/unsubscribe> and no text in the body.          *
***************************************************************************
* If you are having a problem with the IPC TechNet forum please contact   *
* Dmitriy Sklyar at 847-509-9700 ext. 311 or email at [log in to unmask]      *
***************************************************************************