Ian,

You are correct in your observation that 610 does not include 
reflow in the solder processes; however, it is not common 
practice to stencil solder onto a via hole so there is no solder 
applied to a via hole from a reflow process.  A high percentage 
of the time, if not 100% of the time, the via is filled with 
solder due to wave, dip, or drag solder.

The criteria listed in both documents only apply if the via hole 
is exposed to a solder process.  It is not a process indicator 
unless the via hole was exposed to solder and did not wet 
properly per the criteria listed in the specification.  If the 
via hole was never exposed to a solder process there are no 
issues with insufficient solder in the hole.

To answer your specific question, you do NOT need to record any 
of your via holes as process indicators since you do not stencil 
solder onto the via.

Bruce Wooldridge
DSC Communications Inc.
Vice Chairman, IPC-A-610 Task Group
214/519-6170
[log in to unmask]


______________________________ Reply Separator _________________________________
Subject: Via solder fill
Author:  [log in to unmask] at SMTPLINK
Date:    10/05/95 12:42 PM



Greetings Colleagues,

I have a question regarding Interfacial Connections, and an apparent 
disparity between J-STD-001 and IPC-A-610.

Briefly, para. 9.2.5 of J-STD-001 states

"Plated through-holes without leads, including vias, after exposure to 
reflow, wave, dip, or drag solder processing SHALL meet the 
acceptability requirements ...."

However, IPC-A-610 states

".... after exposure to wave, dip, or drag soldering equipment shall 
meet all ......"

Note, no reflow process mentioned in 610.

Vias will not have any solder applied with a reflow process unless the 
stencil is manufactured that way.  None of our stencils has any 
provision for applying solder to via holes.  Does this mean, in order to 
comply, that we have to record every occurrence of this as a process 
indicator?

Thanks in advance,

Ian J Graham,
Quality Manager.
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