History:
We as a board manufacturer usually see customer allowances very similar to
those that Mike Green has described, and for much the same reasons. The
tolerance Nick Koop referenced in IPC-6013 closely resemble those
requirements and offer some common terminology between our specs. Maybe the
unspoken truth here is that these tolerances are sometimes greatly exceeded
by pwb manufacturers since there is no such tolerance detailed in IPC-6012.
New developments:
There are some new concerns today which may necessitate documenting this
allowance. We have seen product built as always but now having BGA and
mini-BGA assemblies mounted. There typically is no issue until these BGA
assemblies are reworked (removed and replaced). The temperatures involved
in the removal are often not well controlled, and the repeated thermal
excursions (often up to 3-4 times), sometimes causes the reflowed solder to
flow. This may lead to lifted or cracked soldermask, allowing the reflowed
solder or even the solder balls to flow into areas they shouldn't, and
causing shorts that are a bear to find.
Why change:
So we now have somewhat marginal assembly practices (especially with the
coming of higher temperatures for lead-free assembly) creating new
requirements for existing pwb manufacturing practices. There are efforts
underway to help define the maximum amount of reworks possible at assembly
without adverse effects on the pwb, which will help. It is my belief that
the need to protect the barrel of these vias is too precious, especially on
high reliability pwbs, to throw out the allowance for soldermask to cover
some amount of reflowed solder and still meet the description of SMOBC.
How do we change:
It is time to document the allowance in IPC-6012 and align with IPC-6013.
With good data we may be able to possibly tighten up the allowance some, I
typically see that .005" would be the absolute minimum that most
manufacturers could live with, and seldom see concerns with .010" in
assembly. With this approximate size, I would expect that the surface
tension of the soldermask would force any reflowed solder to flow into the
barrel of the hole rather than loosening the soldermask under normal
controlled rework scenarios.
My vote:
No to the proposal as it reads.
I would support documentation with approximately .010" tolerance. Maybe
less with data.
Tom Kemp
Rockwell Collins
Collins Printed Circuits
Quality Assurance Manager.
(319)295-1619
John Perry
<[log in to unmask]
G> To
Sent by: [log in to unmask]
IPC-600-6012 cc
<IPC-600-6012@IPC
.ORG> Subject
[IPC-600-6012] Proposed IPC-6012B
Change for SnPb in SMOBC
04/19/2005 11:05
AM
Please respond to
"(Combined Forum
of D-33a and
7-31a
Subcommittees)"
<IPC-600-6012@IPC
.ORG>
Colleagues,
The IPC D-33a Rigid Board Performance Task Group is beginning the
development of an Amendment 1 to IPC-6012 Revision B. Relative to this is
a request to modify and append text in section 3.5.4.7, Final Finish
Coverage (Areas not to be soldered).
Background on change request:
A printed board was found to have small amounts of Tin Lead under the
solder mask with reflow/SMOBC finish. The part has been fabricated using
the selective solder strip process. The customer rejected the parts for
small amounts of tin lead found on bare copper and under the solder mask,
claiming with Tin Lead, the part no longer was Solder Mask over Bare
Copper. There is currently no IPC specification that prohibits such Tin
Lead on the bare copper. However, at some point it becomes a workmanship
issue per IPC 6012B paragraph 3.3.9.
Rationale for change request:
This new accept/reject criteria provides a check and balance for the tin
lead strip process (i.e., the process is not capable of absolute ZERO tin
lead as there is always trace amounts on some circuits) and at the same
time we don't want to be throwing away printed boards that are functionally
fine.
Proposed Change within 3.5.4.7 of IPC-6012B:
3.5.4.7 Final Finish Coverage
Final finish shall meet the solderability requirements of J-STD-003.
3.5.4.7.1 Exposed Copper (Areas not to be soldered) Exposed copper on areas
not to be soldered is permitted on 1% of the conductor surfaces for Class 3
and 5% of the conductor surfaces for Class 1 and Class 2. Coverage does
not apply to vertical conductor edges.
3.5.4.7.2 Tin-Lead under SMOBC
Tin or Tin Lead under SMOBC on areas not to be soldered is permitted on 1%
of the conductor surfaces for Class 3 and 5% of the conductor surfaces for
Class 1 and 2.
If you approve the proposed change without comment, please send your
approval, by May 3rd, to [log in to unmask] If there is a need to comment on
and discuss this within the task group, please respond through this e-mail
forum.
Thanks,
John Perry
Technical Project Manager
IPC
3000 Lakeside Drive # 309S
Bannockburn, IL 60015
[log in to unmask]
1-847-597-2818 (Phone)
1-847-615-7105 (Fax)
1-847-615-7100 (Main)
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