Subject: | |
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Reply To: | (Designers Council Forum) |
Date: | Tue, 15 Mar 2005 11:00:38 -0500 |
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My personal preference is to always try and make the schematic symbol look
like the physical component (same number of pins/side, same pin # sequence,
etc).
In this case it just does not seem practical or possible since the pins are
actually an array beneath the component. I think I'm going with the
partitioned symbol approach as most of you have suggested.
Thanks for the help.
Scott D. Riley
Technical Design Service
607-658-9322 - Office
607-785-1696 - FAX
www.techdesignservice.com
-----Original Message-----
From: James Jackson [mailto:[log in to unmask]]
Sent: Tuesday, March 15, 2005 9:18 AM
To: (Designers Council Forum); Scott Riley
Subject: RE: [DC] Schematics for high pin count BGA devices
Each one has their own preferred ways to do things... so here is another to
consider.
If possible - break up the device into at least 2 'blocks'.
The first one can be just the 4-sided square with pins on the left and
right.
The second can have pins on the top and bottom.
The first would be the I/O, Clock, etc.
The second would be the Power and Ground pins.
This would allow you to jockey the I/O pins to your hearts' content... which
will sometimes change - based upon PCB layout... I.E. - if this pin moved
over here, I could have a better routed board.
(Also - sometimes the engineer will re-compile the FPGA's or CPLD's which
could necessitate changing a logically divided 'based upon function' type of
symbol - but not so with the above method.)
The Power and Ground usually do not change - and can also have their
respective bypass capacitors near them - making for a better visual of what
capacitors go where.
Even at 484 pins - this should fit on a C-Size titleblock sheet.
Regards,
James Jackson
Oztronics
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]On Behalf Of Scott
Riley
Sent: Tuesday, March 15, 2005 7:47 AM
To: [log in to unmask]
Subject: [DC] Schematics for high pin count BGA devices
I'm looking for a little information on the best way to represent BGA
components with a high pin count (EX: 484 I/O) in a schematic. I need to be
able to document a schematic for a board that will have two BGA devices (484
I/O and 165 I/O). Once the customer reviews/approves the schematic I would
extract a netlist and use it to create rats on the layout and for
programmatic comparison.
My assumption is that I will need to create symbols that have all the pins
around the perimeter of a square or rectangle, but was hoping someone could
share their experience on schematics for similar components and if there is
a better/different approach.
Scott D. Riley
Technical Design Service
607-658-9322 - Office
607-785-1696 - FAX
<http://www.techdesignservice.com/> www.techdesignservice.com
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