For component courtyard sizes, this tool will give you courtyard sizes
for wide, normal, and dense placement:
http://www.pcblibraries.com/IPC-7351/

There should be some process for the manufacturing engineer to review
placement just as routing is beginning.  

Spacing rules on copper features should be provided by the board house.
I try to start with as much spacing as possible.  I figure when I move
below 7/7 mils width/spacing, I'm adding at least some cost to the
board.

I base through-hole padstacks on these rules:
http://www.pcbexpress.com/technical/faq.php#drills%20

PCB Express is a cheap fab house, so anyone ought to be able to fab
something built to their guidelines.

CJ


-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
Kitty Hines
Sent: Tuesday, August 28, 2007 2:53 PM
To: [log in to unmask]
Subject: [DC] Spacing Requirements

Hi,
I'm trying to revamp some of the spacing requirements that our
Manufacturing Dept. has decided upon and need some documented proof that
the spacing they "require" is unnecessary.  I tried to find specific
requirements in IPC-2221, but wasn't able to find them.  What I'd like
to
find is spacing requirements for pad-to-pad, pad-to-trace, smd land-to
smd
land.  I'd like to find requirements for solder wave and reflow
processes.
Does anyone know what IPC spec I should be looking at?  Or a reliable
reference I can find?  These requirements would only take Manufacturing
rules into consideration, disregarding any electrical rules.
Thanks for any help you can be,
Kitty

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