Yes, that's what we're doing- I just wanted to make sure you didn't count
my experience as a data point... at least until we get a new set of boards
that the manufacturer believes were made per spec.
The process we're paying for at this time (60% plug of vias with
soldermask) represents a 1-2% cost increase with our current manufacturer,
instead of a 5%+ cost increase- so hopefully it works. IPC specs (and
experience of others in this thread) seem to indicate it won't be
particularly successful, or scale.
Tom
On Mon, Dec 19, 2016 at 9:29 AM, Jack Olson <[log in to unmask]> wrote:
> Thanks, Tom.
>
> My question was related to an alternate method to AVOID the cost of
> plugging/capping the vias
>
> Unless I misunderstood what you are saying,
> If you are paying for that process and you still have solder wicking
> through,
> you should be investigating that with the bare board fabricator,
> (or at least get your money back)
>
> Jack
>
> On Thu, Dec 15, 2016 at 10:45 AM, Tom Brendlinger <
> [log in to unmask]> wrote:
>
>> We recently used the following notes to attempt to do precisely what
>> you're describing:
>> 12.2 All vias 0.020" in diameter or less shall be plugged from top side
>> prior to primary soldermask application per IPC-4761 Type III. Plug
>> material shall be approved by Levant engineering before production begins.
>> 12.3 Plugs in vias shall not protude above top of hole.
>> 12.4 All plugged vias shall be filled at least 80% with fill.
>> 12.5 Via plug integrity, fill percentage and protrusion shall be
>> confirmed with a microsection of a representative quality conformance
>> coupon
>>
>> However, after soldering about 30% of the at-risk holes had solder
>> flow-through. We didn't see bumps, just a thin layer of wetting, but we
>> only had 16 boards populated in this run so I don't think we have enough
>> data to show that we never would have that issue.
>>
>> I am currently working with our PCB manufacturer to identify what
>> happened, but in my opinion this isn't a fully manufacturable solution. I'm
>> attempting to solve the same problem that you are, so I'm absolutely
>> interested in any other way to do this.
>>
>> --
>> Tom Brendlinger, CID
>> Electrical Engineer
>> Levant Power / ClearMotion Inc
>> Woburn, MA 01801
>>
>> On Thu, Dec 15, 2016 at 11:10 AM, Jack Olson <[log in to unmask]> wrote:
>>
>>> I'm looking at the various options for tenting/plugging/capping vias in
>>> IPC-4761 (Via Protection Guidelines). None of the options seem to address
>>> the thermal vias in power pads.
>>> We are trying to:
>>> 1) have a solderable pad, apply paste on that side (of course)
>>> 2) prevent solder from creating bumps on the heatsink side (of course)
>>> 3) avoid the cost of plugging/capping
>>>
>>> IPC-4671 states that all forms of one-sided via protection are NOT
>>> RECOMMENDED.
>>>
>>> So here's the question - I know I have seen a picture of a thermal pad in
>>> an IPC document where I could see vias with green mask material in them
>>> on
>>> the paste side (the component side), but the green stuff was only in the
>>> holes, which left the thermal pad exposed for soldering.
>>> I don't think this would be called TENTING because there's no mask on the
>>> pad. but is this an acceptable practice? Can I instruct a bare board
>>> fabricator to put mask in holes from the top side, but keep the pad
>>> clear?
>>> (I can't remember where I saw the picture!)
>>>
>>> If that's NOT an accepted practice, is there a way to design the hole big
>>> enough to plate but small enough to prevent solder flowing through the
>>> other side of the board? I couldn't find a discussion of that in the
>>> TechNet Archives
>>>
>>> thanks,
>>> Jack
>>>
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>>
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