One option to lower solder wicking on opposite side could be to increase via diameter. For example to 20mils. Any one has same experience?
rgds
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Message du 13/09/12 00:07
De : "Fred Dark"
A : [log in to unmask]
Copie à :
Objet : Re: [DC] Vias under a QFN package (Thermal Refief)
We use 8mil vias with no issues in assembly process... processing component side and or solder side first... Doesn't matter..! 10mils is good also
depending how the board is ran in the assembly process...
Regard's, Frederick Dark Jr.
Manager Senior PCB Designer
Crestron Electronics, Inc.
22 Link Drive Rockleigh N.J. 07647
P:201.750.7004 ext.11320
F:210.767.5772
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-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Brooks, William
Sent: Wednesday, September 12, 2012 5:37 PM
To: [log in to unmask]
Subject: Re: [DC] Vias under a QFN package (Thermal Refief)
Hi Kitty,
I believe this is a common situation that is experienced over and over again by many pcb designers...
I'm not sure if IPC has a 'standard' way of dealing with this issue.
Personally, I think in this situation I would approach the problem from a practical point of view.
If I am designing a board with a part that has a thermal pad in the belly of the IC I am going to be concerned with making a good solder joint and getting the
heat out of the part first. I have found that lead based solders have a lot of surface tension and tend to wick into holes pretty well... however, when the hole
diameter gets small enough, it tends to slowly wick into the hole and plug the hole with solder and not wick much beyond that... the capillary action of the
smaller hole diameter restricts the flow of solder to a large extent. Something like about an 8 to 12 mil hole ought to work very nicely... So if the Assembly folks
put enough solder paste on the part to compensate for the partial wicking the part gets both a good solder joint and a good thermal transfer to the thermal
pad.
If I had mixed technology, i.e. through hole and surface mount devices on the board... like it sounds that you do, I would have a stencil company make a wave
soldering fixture to cover the back side of the board so as to prevent splashing the back side of the thermal pad with the solder wave, preventing a second
reflow of the solder.
That might take care of this problem for you... :) The protective stencils can be a little pricey, but it can be a one-time cost that you can spread out over the life
of the board build...
:)
Hope that helps... :)
William Brooks, CID+
Senior MTS (Temp)
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax: 760.918.8332
Mobile: 760.216.0170
E-mail: [log in to unmask]
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Kitty Hines
Sent: Wednesday, September 12, 2012 2:12 PM
To: [log in to unmask]
Subject: [DC] Vias under a QFN package (Thermal Refief)
Hello-
I'd like to ask how some of you are handling vias under a QFN package.
What I'd like to do is plug them completely from the bottom with epoxy.
Many high volume manufacturers will only use solder mask for plugging vias, or charge a 10% increase in cost. The vias are required for thermal relief
under the part, so solder mask must be left open on the top. These vias need to be filled or tented from the bottom to prevent solder from wicking up during
the solder wave process, after reflow. So far, using only solder mask for plugging isn't working out very well. I haven't been able to find a simple solution,
everything I've read basically said yes, this is a problem. But haven't found any solutions. One company has offered a LGA pattern for an identical part, but
this land pattern has even more vias exposed under the LGA package, also for thermal refief. Any suggestions?
Thank You So Much,
Kitty
Kitty Hines
The Chamberlain Group, Inc.
(630)516-6655
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