I have seen documentation before saying (and just confirmed from my senior
hardware engineer that it is bad practise to run tracks under electrolytic
caps because they can leak round the bottom during normal use & etch through
to the track causing damage etc.
I'd assume that the same can then happen for the IC being under it.

It would also make it harder to replace the IC so if your going to do it I'd
suggest making the holes & lands of the cap pads bigger than normal so that
it can be removed/replaced without the lands lifting etc.

Matthew Lamkin.




-----Original Message-----
From: Richard [mailto:[log in to unmask]]
Sent: Wednesday, January 21, 2004 9:44 AM
To: [log in to unmask]
Subject: [DC] Component stack up / is it OK?


Hi,
I'm working on a board that has a shortage of real estate.
By far the best placement (electrically, ease of assembly etc.) for a large
through hole cap and a 14-pin SOIC on this board would be to have the IC
directly underneath the CAP.
The IC would get reflowed with the other SMDs, and then the CAP would get
waved with the other THDs.
I plan to add vias (and maybe even the silkscreen) on the bottom so that all
the pads can be probed.
My question is if this is a bad practice?  Will the IC have contaminates
trapped on it during assembly because of the CAP?  Environmental issues
aren't a concern, and there is no chance of anything shorting in this
orientation.
I hope it's OK to do this.
Any answers are greatly appreciated.
Thanks,
Richard

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