Steve,

This Pre-Design Checklist (sorry, the check boxs didn't come accross) is
in "some" use here at EFData...

I'm currently revising it along with creating worksheets (i.e. - for
proposed layer stackups).  Obviously it is geared somewhat specifically
for us.  Bear in mind that this facility uses PADS PowerPCB, OrCAD SDT
(DOS-based), and CCT.  We're moving to Viewlogic for schematic capture.

Jason

        Board Outline Drawing
                Keep-Out Areas Defined                                  Height-Restricted Areas Defined
                Connector(s) XY/Pin 1 Orientation Defined               Mounting Holes and Board
Cutouts Defined
                Board Stiffeners Defined                                        RF Shields Defined
                User-Accessible Jumpers/Switches Defined                Thermal Considerations
Defined

        Proposed Layer-Stackup
                Total Board Thickness                                   Plane Layers Definition
                Total Number of Layers                                  Special Board Material & Dielectric
Thicknesses

        Critical Nets (Excel spreadsheet for this available upon request
accompanied by PADS ASCII netlist)
                Daisy-Chain (i.e. - clocks) Routing                     Starburst (i.e. - data/addr
bussing) Routing
                Required Impedance(s)                                   Required Impedance(s)
                Layer/Via Preferences/Restrictions                      Layer/Via
Preferences/Restrictions
                Maximum Stub-Lengths                                    Maximum Stub-Lengths
                Differential-Pair Routing                                       Min/Max Trace Lengths (or delays*)
                Source/Termination Definitions                          Allowable Crosstalk Rules*
                Termination Requirements                                Allowable Parallelism Rules*
                Min/Max Trace Lengths (or delays*)                      High-Current Nets
                Aggressive Nets (Talkers)                               Aggressive Nets (Talkers)
                Noise Susceptible Nets (Listeners)                      Noise Susceptible Nets
(Listeners)
                Allowable Crosstalk Rules*                              GNDing/Stitch Via Issues Addressed
                Allowable Parallelism Rules*                            Additional Shielding Around Traces

        Component Placement Issues
                Proposed Layout Sketch                                  Redefinable Xylinx and/or Connector Pinouts
                Clock Oscillator vs. Termination                                Bussing Related Component Flow
                Fixed Component Locations                               Resolution of GND Vias that Violate
Standard
                High Tolerance Filters for Microwave                    Footprints (i.e. - fet
transistors & caps)
                Pin & Gate Swapping Restrictions                        Reference Designator Re-Annotation
Allowed

        ICT Test Point Requirements
                Fixtured for Top/Bottom or Both                         Devices Identified for Boundary
Scan
                Cluster Test Definitions for RF Circuits                        Nets Excluded from Test
Points

        New Parts Requests Submitted

        Work Order Request Submitted

        OrCAD Database Diskette Submitted
                OrCAD Schematic File(s)                         Gap File (using FindGap Utility)
                Bill-of-Materials (BOM in CSV format)                   Cross-Reference (XRF) File
                Library (LIB) File                                              PADS ASCII Netlist (ASC) File
                OrCAD ERC File (per OI specification)                   ERC Label Report (using
ReadERC utility)
                Schematic Pen Plots                                     PCB Design Traveler Started



>----------
>From:  ST@Electro-CADD,Inc.[SMTP:[log in to unmask]]
>Sent:  Friday, August 15, 1997 7:41 PM
>To:    [log in to unmask]
>Subject:       Design Check List's (Please submit yours)
>
>Hello to all out there in the Design World!
>
>   IMHO I think it would be of great service to all in this forum if we
>shared our Schematic/Layout checklist's as well as non-propriatary
>fabircation and assembly notes, for a varity of designs, from simple double
>sided to intense multi-layer including MCM,BGA,FLEX,RF,etc..  and compare
>the possibilities of how it may help others in our field.  I am still
>working on mine, and will post it to this group within the next day or two.
>I would appriciate any comments or criticism.  This is something that has
>usually been a guarded secret, but now that the world is communicating this
>way, LET'S SHARE!
>
>                        Thanks in advance,
>
>                        Steve Toothacre
>                        Electro-CADD, Inc.
>                        Poway, CA 92064
>                        (619) 748-4223
>Steve Toothacre a.k.a. Pork_Chop
>A PCB designer who enjoys the challange of a complex design
>
>