Hi all !! I just got into a little debate about via fill. Say for instance you get some boards in at recieving where upon inspection, you see via's that have mask partially in the holes. The via's were not intended to be tented, but on the same hand the artwork was never relieved to prevent the vias from being covered with mask. The vias are open, but do have mask partially down inside them as it appears the mask used was a LPI that doesn't completely tent vias well. I was asked if this was a problem, I said no...unless the board was going to go to ICT where vacuum was going to be needed, or maybe good via fill was needed to have good probe contact. But since the mask was not relieved, it's not a problem...I interpret that as the via's were never meant to be filled. I was then asked will some of them fill? I said maybe some will, but probably most won't. Then I was told that according to 9.2.5 (page 17) in the J-STD-001B the vias HAD to meet Figure 9-2 (on page 18) of at least 75% fill. I said not all...the via's were never intended to be filled, whether they fill or not is not a problem at all. It won't affect reliability or function if they do, or do not fill. I was told I was wrong....am I? Thanks! -Steve Gregory- ############################################################## TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c ############################################################## To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body: To subscribe: SUBSCRIBE TECHNET <your full name> To unsubscribe: SIGNOFF TECHNET ############################################################## Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information. If you need assistance - contact Gayatri Sardeshpande at [log in to unmask] or 847-509-9700 ext.5365 ##############################################################