I see that Franklin has already answered your question
about the white tin chemical reaction and application method. I agree
with his caution regarding mask and/or legend peel, having experienced the
same thing. There are ways of fixing the peeling problem without
having to change hardener, however. Any PCB shop setting up an
immersion tin process needs to perform adequate tape tests and
implement controls before adding this process to their Final
Finish list.
As to your other questions, PCB makers differ in their
handling of etch compensations. Some like the designer to add the etch
factors up front, but most would probably rather do it themselves.
Because each of us have slightly different processes, material and equipment
we may have slightly different needs insofar as etch factors are
concerned. One shop may like to see 1 mil added (for 1 ounce copper
surfaces) and another shop may like slightly more or less. It's all a
matter of knowing your own process characteristics.
I would venture to say that most shops would prefer
that etch factors are not added up front. Most of us would rather
do this ourselves.
Hope this helps a little.
Mark Mazzoli
Engineering Manager
Circuit Technologies
3622 Clearview Pkwy.
Atlanta, GA 30340
770-458-1700
----- Original Message -----
Sent: Friday, July 23, 1999 5:38
AM
Subject: [TN] White Tin land
patterns
With respect to solder protect ant on PWB land patterns,
what is "white tin" ?
- Is it only tin and alloy or combination of metal and something
else?
- How is it applied to the land pattern?
With respect to
etch back on 1 oz copper. We would like to design boards with lands, for
20 mil pitch QFPs, that measure between 10 and 11 mils wide.
Some of our board houses ask us to bump our fab drawings to 12 mil while
others asked us not to. Any opinions out there?