Hello Technetter's: Hey, does the following look familiar? I sent this problem out last week but was 0 for 1743. Any responses via Technet or direct would be greatly appreciated Our BGA process (for a mixed-tech pcb) historically was to: fill (solder) the vias with a bottom-side stencil place & reflow the BGA on the top-side mask the BGA location and wave the thru-hole components Note: via fill required for In-circuit Test for their probes and/or for vacuum. Question: What is the risk of exposing the BGA vias to the wave? ie: reflow the bga, cause voids, or ???? Thanks in advance, Al Kreplick Sr. Mfg. Eng. Teradyne, Inc Boston, MA 617-422-3726 ################################################################ TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c ################################################################ To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body: To subscribe: SUBSCRIBE TechNet <your full name> To unsubscribe: SIGNOFF TechNet ################################################################ Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section for additional information. For technical support contact Hugo Scaramuzza at [log in to unmask] or 847-509-9700 ext.312 ################################################################