Bob, Maybe you don't recognize my name, but I believe yourself, Bill Moorhouse and I corresponded together on some old Norden PWB/heatsink assemblies built at the "old" N.A.P.C. This was about time that Gary Cormack was in Purchasing and subsequently screaming at Tyco for late deliveries. I still regularly correspond with Phil Milite. Anyway - I'm connected to IPC Technet and received your mail. If you have specific questions concerning VME heatsink applications, I may be able to help you. We've got full capability at Tyco to machine 3-dimensional heatsinks, procure plating at qualified sources as well as offering an array of bonding adhesives for attachment to the PWB surface. When the time approaches and you're ready for technical advice on heatsink technology, please feel free to call me. Take care. Sincerely, Ken D'Angelo Heatsink Process Engineer Tyco Printed Circuit Group Value Added Systems Division T: 860.684.8000 x4332 F: 860.684.0714 -----Original Message----- From: Vanech, Bob [SMTP:[log in to unmask]] Sent: Friday, October 09, 1998 9:58 AM To: [log in to unmask] Subject: [TN] digital pwb design survey To all.. A few days ago, we had a lot of activity related to pwb' design cycle/requirements. I've been having an ongoing battle with those, that have no idea what we do, but are experts in what we do, you all know who I mean. I keep hearing that "These types of designs are completed much quicker and cheaper by other companies! Why can't you be competitive?" When I question them on their source of information, it's usually, "My project buddy at Company ABC said so!" When I ask for the details, such as size of board, number of layers, technologies, etc., it becomes very evident that we are comparing apples to bananas, pears to grapes, you know where we're going with this. When I talk to my counterparts or the "designers in the trenches", I hear that they are experiencing similar comparisons in their workplace. So, it seems as if we are trying to justify our hours and calendar time against a nonexistent target.... Great for the bean-counters that are kicking the c##p out of us, but not really fair to the guys/gals doing the REAL work. Soooooo, maybe it's time to get together and collect some HARD, REAL data on what we do, so the next time the hot shots try to blow smoke up our butts, we'll have facts, not fictions to justify our design cycle. I'm including a list of design parameters, similar to those listed in the e-mails, that will allow us to INTELLIGENTLY evaluate what it takes to do a design. Obviously, this will not be true for all designs, but at least it will give us a general idea of what we did, with what we where given, what we outputted and what kind of time it took for a family of SIMILAR designs. Of course, we might have those that will, as one commented, toot toot toot their horn with some exaggeration. However, if enough replies come in, one can throw out the high's and low's and go with the average. At least it can be a starting point. So, if you want to fill out the survey and send it Directly back to me, I will try to put it in a form that makes sense and send it back to technet for all to review. If I have missed any really important items, a subsequent survey can be initiated. If this works and the net finds it's helpful, then other families of surfaces can be surveyed. Thanks in advance and have a great weekend!!! Regards, Bob Vanech NOTE: FOR THIS FIRST CUT, PLEASE, ONLY SUBMIT DESIGNS THAT ARE BETWEEN 9.3 x 6.7 (APPROX. VME) to 9.3 x 10.2. EXAMPLE YOUR DESIGN -------------------- ------------------------------ CLASSIFICATION/ BOARD CLASS 3 TYPE PER IPC-2221/2222 /TYPE 5 SIZE 9.25 x 10.18 TYPE OF DESIGN DIGITAL/TTL/ECL/SMT THERMAL CONSTRAINTS NUMBER OF COMPONENTS MICROCIRCUITS 50 DISCRETES 350 OTHER UNIQUES NONE TYPE OF MICROCIRCUITS 132&160&224 PIN GATE ARRAYS/ 24 PIN QUAD FLATPACKS/16 & 24 PIN FLATPACKS TYPE/PIN COUNT OF 280 PIN SMT/ 2 @ CONNECTORS 20 PIN SMT NO./DESCRIPTION OF LAYERS 15 TOTAL LAYERS TOP/BOTTOM COMPS/PADS/ SIGNAL (SEE BELOW) CRITICAL 2 FOR TTL/2 FOR ECL NON-CRITICAL ROUTED ON TTL/ECL PLANES 9 SPLIT PLANES NONE NO. OF PINS/NETS 2250/420 TRACE/SPACE (MAJORITY) .007/.0055 % OF CRITICAL ROUTES 50% % OF ROUTING TECHNIQUE MANUAL 100% AUTOROUTE NONE AVG NO. OF NET LIST/ 4/3/5 PLACEMENT/ROUTING ITERATIONS AFTER REL. TYPE OF ROUTING o IMPEDANCE * MATCHED LENGTHS FOR TRUE & COMPS * CRITICAL HI-SP CLKS o TERMINATION RES. ON ALL DIFF. PAIRS * MIN. ECL/TTL SHADOWING ON ALL LAYERS * MIN. CROSSTALK * STITCHING OF GROUND PLANES TO REDUCE RETURN CURRENT PATH TASKS INCLUDED IN * GENERATE LAND PATTERNS DESIGN CYCLE * GEN. PARTS LIST FROM ELEC. SCHEMATIC * GEN. PLACEMENT FROM ELEC. PRELIM. LAYOUT * GEN. THERMAL DATA * ROUTE CRIT. SIGNAL/ REVIEW BY ELEC./RE- ROUTE IF REQUIRED * SAME AS ABOVE FOR REMAINING ROUTES ' o GEN. DXF FILES TO DFT FOR PWB/ASSY DWGS o GEN. GERBER FILES FOR PHOTOTOOLING * CHECK PWB DWG VS FILM * CHECK ASSY DWG VS PL * GEN. CAM AIDS * REL ALL DWGS/FILES TO CONFIG. MANAGEMENT DESIGN CYCLE (WORKING DAYS) o 90 CAL. TIME - INCLUDING CHANGES o 130 IN REL. DATA/ CHECKING/ REVIEW- ING BY OUTSIDE DISCIPLINES/STOP WORK BY PROJECT ORDERS COMMENTS * CHANGED FROM TOP H'SINK TO BACKPLATE * STOPPED WORK/2 MONTHS FINAL PIN OUTS OF 132GA NOT DEFINED FROM VENDOR **************************************************************************** *************************** COMPLETE IF YOU OFF-LOAD DESIGNS TO DESIGN SERVICES: DATA GIVEN TO OUTSIDE o STATEMENT OF WORK DESIGN SERVICE * CRITICAL DESIGN GROUND RULES * PLACED/NET LIST DATA RECEIVED * ROUTED ELECTRONIC DATA BASE OF ALL FILES, COMPATIBLE TO OUR SYS. * DXF FILES FOR DRAFTING OR PWB/ASSY DWGS ON OUR FORMAT DAYS SAVED BY OFF-LOADING o ADD 1-2 WEEKS TO CYCLE TO DESIGN SERVICE THANKS ################################################################ TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c ################################################################ To subscribe/unsubscribe, send a message to [log in to unmask] <mailto:[log in to unmask]> with following text in the body: To subscribe: SUBSCRIBE TechNet <your full name> To unsubscribe: SIGNOFF TechNet ################################################################ Please visit IPC's web site (http://www.ipc.org <http://www.ipc.org> ) "On-Line Services" section for additional information. For technical support contact Hugo Scaramuzza at [log in to unmask] <mailto:[log in to unmask]> or 847-509-9700 ext.312 ################################################################ ################################################################ TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c ################################################################ To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body: To subscribe: SUBSCRIBE TechNet <your full name> To unsubscribe: SIGNOFF TechNet ################################################################ Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section for additional information. For technical support contact Hugo Scaramuzza at [log in to unmask] or 847-509-9700 ext.312 ################################################################