Hi Scott-- There are several problems when using multiple plated-through holes for high current applications. 1 - for "simple" designs, as long as the copper's cross-sectional area of the via is >> than the cross-sectional area of the ingress/egress conductors, then the design charts for thermal rise above ambient are applicable. This is because if the via's cross-sectional area is >> than the conductor's, then the resistance of the via will be proportionally less than the conductor's, heating will be less, and the end result will be the thermal rise will be less. 2 - if the cross-sectional area of the plated-through hole is the same as the conductor's, then there may be a local increase due to the length of the via (board thickness) and this will result in a local increase in temperature, so if this is the case then you should consider using the "internal" charts for doing the design. 3 - if the "signal" currents are dc (direct current) or low frequency (like power line) then the "routing direction of the conductors ingress/egress directions becomes a concern, especially with high pulsed energy applications. You need to do a series/parallel resistance/inductance network analysis to determine where the maximum current will flow -- if by a "fluke" all currents in the plated-through holes are equal (under all current applications), then you've got an acceptable design as the currents are evenly distributed. An example of this would be a "parallel rail ladder" where the current enters one "rail" end, passes through the "rungs" to the "other rail" and exits the network on the opposite end of the ladder from where the current entered. A worst case is when the currents enter and leave the ladder on the opposite rails on the same end of the ladder. In this example the "loop resistance/inductance" of the first ladder rung (via) will carry the most current, the additional ladder rail resistance/inductance reduces the current in the second rung/via, etc. What can/will happen is that the first via will "blow-out", then the next, etc. This is not a desirable design feature. One way to get out of it is to use a "star" like pattern, especially with mounting fasteners (such as screws bolts, stud-mounted semiconductors, etc) with the fastener in the "center" and the via's located on equal radii. To my knowledge, there is no design data/requirements for your application, if there is it's all held "company proprietary". We used the above for about 30+ years in my previous life's employment without any known failures in applications of dc currents of <200 A, and pulsed currents of <2 kA with a few ns pulse widths. Bottom line -- treat is as a complex electrical interconnection network, and go for uniform voltage drops and current distribution over the range of application frequencies. Hope this helps, other wise contact me and I'll provide some additional information. Ralph Scott Holthausen wrote: > Hey TechNeter's > > Does anybody have an equation that could help a person determine the > current handling capability of through hole vias? Our practice has > normally been to use multiple vias to connect components with high current > paths to plane layers. However, that isn't good enough for one of our > engineers who wants more than an approximation, and wishes to find out > whether we are putting more vias on the board than we need to. > > Thanks, > Scott Holthausen > > ################################################################ > TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c > ################################################################ > To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body: > To subscribe: SUBSCRIBE TechNet <your full name> > To unsubscribe: SIGNOFF TechNet > ################################################################ > Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section for additional information. > For technical support contact Hugo Scaramuzza at [log in to unmask] or 847-509-9700 ext.312 > ################################################################ -- Ralph Hersey Ralph Hersey & Associates 3885 Mills Way Livermore, CA 94550-3319 PHN/FAX: 925.454.9805 e-mail: [log in to unmask] ################################################################ TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c ################################################################ To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body: To subscribe: SUBSCRIBE TechNet <your full name> To unsubscribe: SIGNOFF TechNet ################################################################ Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section for additional information. For technical support contact Hugo Scaramuzza at [log in to unmask] or 847-509-9700 ext.312 ################################################################