Hey TechNeter's

Does anybody have an equation that could help a person determine the
current handling capability of through hole vias?  Our practice has
normally been to use multiple vias to connect components with high current
paths to plane layers.  However, that isn't good enough for one of our
engineers who wants more than an approximation, and wishes to find out
whether we are putting more vias on the board than we need to.

Thanks,
Scott Holthausen

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