Hi everyone! I would be appreciative of any help whatsoever on the following subject: I am currently assessing the suitability of using no-clean flux technology on Class 3 Electronics - Military. Our current capability is double sided Reflow (forced convection), Vapour Phase & Wavesolder. We assemble onto the following substrates - FR4, Copper Invar Copper, Ceramic. SMD design is currently @ 0.02" pitch, whilst currently evaluating 0.016" & BGA. I am trying to identify all areas of concern with using no-clean flux to enable me to come up with a plan for addressing/proving the process for suitability/reliability. I believe I have identified the main areas but would be interested in the experience/views of my counterparts in this field. ################################################################ TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c ################################################################ To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body: To subscribe: SUBSCRIBE TechNet <your full name> To unsubscribe: SIGNOFF TechNet ################################################################ Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section for additional information. For technical support contact Hugo Scaramuzza at [log in to unmask] or 847-509-9700 ext.312 ################################################################