Return-Path: <[log in to unmask]> Received: from simon.ipc.org ([168.113.24.64]) by mail1-gui.server.virgin.net (Post.Office MTA v3.0 release 112 ID# 0-123U50000L2S50) with SMTP id AAA9639 for <[log in to unmask]>; Thu, 20 Mar 1997 01:38:14 +0000 Received: from ipc.org by simon.ipc.org via SMTP (940816.SGI.8.6.9/940406.SGI) id TAA23198; Wed, 19 Mar 1997 19:11:13 -0800 Resent-Date: Wed, 19 Mar 1997 19:11:13 -0800 Received: by ipc.org (Smail3.1.28.1 #2) id m0w7Vds-000BC5C; Wed, 19 Mar 97 18:23 CST Resent-Sender: [log in to unmask] Old-Return-Path: <[log in to unmask]> Date: Wed, 19 Mar 97 16:33:38 PST From: "TOM BRESNAN" <[log in to unmask]> Message-Id: <[log in to unmask]> To: [log in to unmask] Cc: [log in to unmask] Subject: Re[2]: Pulse plating of copper and tin/lead Resent-Message-ID: <"Ci7pe1.0.9QC.-D8Cp"@ipc> Resent-From: [log in to unmask] X-Mailing-List: <[log in to unmask]> archive/latest/11219 X-Loop: [log in to unmask] Precedence: list Resent-Sender: [log in to unmask] X-Mozilla-Status: 0001 Another option would be to panel plate, then print and etch the outer layers (assuming HASL or other finish) ______________________________ Reply Separator _________________________________ Subject: Re: Pulse plating of copper and tin/lead Author: [log in to unmask] at INTERNET_GATEWAY Date: 3/19/97 3:57 PM >I am working to resolve a problem in pattern plating a panel which has a ground >plane on one side (40% plated panel area) and pads on the back side (6% plated >panel area). We use modern DC rectifiers, one for each side, which share the >cathode connection. The panels overplate the back (6%) side even with the >corresponding rectifier turned off. Our only solution was to place current >robbers on the back side which are selectively etched off in a later operation. >I have been given information that "pulse plating" could allow us to plate this >design with out any modifications to the plating areas. My question is: > >1. Does anyone currently use "pulse plating" in a pattern plating operation? >2. Would this technology make plating this type of unbalanced design easier? > > >Thanks, Rick Haynes > Texas Instruments Printed Circuit Resources > 512-250-7823 [log in to unmask] > Hi Rick, Have you thought of panel plating the copper and then imaging to pattern plate the tin-lead. We do this on some unplateable designs and it solved the problem completely. Paul Gould Teknacron Circuits Ltd *************************************************************************** * TechNet mail list is provided as a service by IPC using SmartList v3.05 * *************************************************************************** * To subscribe/unsubscribe send a message <to: [log in to unmask]> * * with <subject: subscribe/unsubscribe> and no text in the body. * *************************************************************************** * If you are having a problem with the IPC TechNet forum please contact * * Dmitriy Sklyar at 847-509-9700 ext. 311 or email at [log in to unmask] * *************************************************************************** *************************************************************************** * TechNet mail list is provided as a service by IPC using SmartList v3.05 * *************************************************************************** * To subscribe/unsubscribe send a message <to: [log in to unmask]> * * with <subject: subscribe/unsubscribe> and no text in the body. * *************************************************************************** * If you are having a problem with the IPC TechNet forum please contact * * Dmitriy Sklyar at 847-509-9700 ext. 311 or email at [log in to unmask] * ***************************************************************************