We're updating our design guidelines and a question has come up. We need to know the clearance between a scored edge and components, both SMT and PIH. Certain folks within the company have complained that components will be stressed when depaneling scored cards after assy, although they make this assumption without data. This is creating an atmosphere of avoiding scoring at all costs, even when it makes sense otherwise. Others say that the stress will be most centered on the internal layer at the edge, since the score leaves only that as a web. This presumably would limit stresses on the parts. Cards are usually mixed technology with SMT on one or both sides, .062 thick with a nominal score of .023 deep, leveling a web of .014. The score is usually 60 degrees. Can anyone shed some light on this (with data, please)? *************************************************************************** * TechNet mail list is provided as a service by IPC using SmartList v3.05 * *************************************************************************** * To unsubscribe from this list at any time, send a message to: * * [log in to unmask] with <subject: unsubscribe> and no text. * ***************************************************************************