From a reliability standpoint, a flag is only a potential problem as a potential shorting path, thus 2000A and ANSI/J-STD-001 would only reject when the flag (or any other conductive element) can or does reduces the spacing between conductive elements to less than the design allowable elecrical spacing: Violation of minimum design electrical spacing. This condition includes potential movement of conductors (including conductive part bodies, leads, wires, etc.), solder balls, excessive solder and bridging. Note that design electrical spacing was taken to include the "Z" axis as well (ie. can't violate the "envelope" for the hardware). Many people further reduce this as a "safety" item (ie. if it's big enough to "stab" someone it should be removed.) Jim Maguire Boeing ______________________________ Reply Separator _________________________________ Subject: ASSY-Flagging Author: [log in to unmask] at esdigate Date: 5/13/96 10:43 AM (This is a re-do of an inquiry sent Friday, in case it went nowhere. I've received no replies and we had a mail-server problem, so I thought I'd try again) I've been tasked with justifying the enforcement of a long established internal requirement, here at PBNI. For as long as I can recall, we have been considering solder flagging (aka icicles, solder spikes) a rejectable condition, even when a solitary occurrence of as little as 0.8 mm. (We based this rejection upon workmanship standards that we adopted from a sister organization with a much more Class 3 and military orientation). As we are manufacturing Class 2 products, and are re-evaluating the adopted requirements, this 'reject' comes into question. I'm reviewing ANSI/J-STD-001A and IPC-A-610B this morning, I find no reference to this condition other than that shown in Figure 4-17 of the latter. I certainly don't object to loosening up on our present standard if it is not justifiable, but I can't help the feeling that I'm missing something. Am I ? An anticipatory ...Thanks !