Having all the components line up nice and neatly on the PWB improves manual "inspectionability," and improves solderability using an IR reflow process. However, most contract assemblers are using convection reflow which reduces the shadowing effect. The problem is just what you had encountered, non-optimization of trace routing. If the engineer is developing a high-speed circuit, they just may be SOL. Don't forget to point out to the engineer that layer-count could increase, which would increase the cost of his board (maybe unnecessarily). This topic is not good to make generalizations. It really comes down to the design at hand. In addition, you should not be prohibited from placing passive chip components on the secondary side of the PWA. The person(s) requiring this may be concerned about electical testing of the PWB which would require simultaneous, double-sided testing because of the existance of SMTs on two sides. As good design practice, you really should attempt to place all components on one side of the PWA. There are many "hidden" costs when components are placed on two sides viz a viz one side. However, you shouldn't be PROHIBITED. Regards, John R. Kretsch, P.E. Engineer, Design Assurance [log in to unmask] ______________________________ Reply Separator _________________________________ Subject: Design questions Author: [log in to unmask] at internet-mail Date: 06/20/96 23:10 All, I don't see much discussion on just plane old design issues. I thought I would throw out a few topics and see if anybody is interested in discussing them. I am crossposting this to Pcad users and IPC Designers Council. Has anybody been using SMT Plus land patterns? They are advertising a lib. for P-Cad. How do they compare to the IPC 782 Patterns? What are you doing as far as via's and conductors under SMD components? I noticed the P-Cad lib has keepouts under the chip components. I have been routing traces under SMD and have not had any problems. Has anyone needed to provide a glue dot file for mfg? I noticed that P-Cad has that capability but I have never had to provide one in the past. It was always created from the placement file. Silk Screen legend sizes seem to be very large on most commercial lib's compared to what I have been using. I seem to get away with .008 width and sometimes down to .060 height. What is your experience? I have just finished a Design for a client that demanded that all components be orientated in the same direction and also all of them lined up, nice and neat. Great idea if I would have had twice the board area to work with. I know the desireability of this but I also like to think form follows function. Many of the original reasons for doing this are obsolete. The board is finished now but I just know placing the parts for optimal routing would have resulted in much shorter runs, and a more functional layout. What is your opinion? How are you doing it? I also was prohibited from putting chip caps on the solder side, even though I routinely do it with other designs. Are any of you designing boards that are waved with chip caps on the solder side? Regards Fred Pescitelli Phoenix Designs 1285 Turner Rd. Lilburn, GA 30247 [log in to unmask] 770-923-3465