Mail*Link(r) SMTP FWD>Analog guard rings Hi David, Technically you not want to bridge the electrical spacing between the guard rings and input terminals; and depending on how critical the design requirements, you also should avoid doing it on the internal layers. If you use solder resist (in lieu of a good conformal coating) it will absorb moisture and collect surface contaminants that will bridge over the guard rings and provide an alternative path for leakage currents/voltages between the input terminals and adjacent conductive patterns/components. The following is more information that expands on the design considerations for guard rings that I did in Chapter 13, of the 4'th edition of the Printed Circuits Handbook, edited by Coombs. You will also need to consider adding guard rings around the input terminals in the power/ground layers if you are using PTH/IMT (plated-through hole / insertion mounted technology). Even with SMT, you may need to consider "isolating" the power/ground plane directly underneath and adjacent to the SMT lands and electrically connecting it to you guard rings. Effectively, what you are trying to do is to form a "Faraday Cage" around the critical input circuitry to isolate the contents for all undesired voltages. As you are aware in using guard rings, it cannot be overemphasized about using a low-impedance voltage source for the guard ring(s) (or Faraday Cage) that follows the input voltage and minimizes the differential voltage between the guard ring and op-amp's input signal. As we know from Ohm's Law electrical theory, if there is no voltage difference, there is no current - reguardless of resistance -- and that's the goal of guard rings, follow the input voltage at the op-amp terminals (which for non-inverting (buffer) amplifiers may include additional components that are at the same voltage as the input signal), especially with differential input instrumentation amplifier signals . If the "bulk" resistance of the base material is a concern, then include a "ring" of PTH's around the input terminals (in the guard rings) between all internal conductive patterns (layers). This controls the leakage currents/voltages between PTH barrels and other internal conductive patterns. Check to see if the op-amp has an alternative "package" with a pair of un-used (no-connection) terminals adjacent to the input terminals. If they do, try to use it because this enhances the use and addition of guard rings by providing additional space around the critical input terminals. One of the other areas of concern for "serious" printed circuit designs are the balance terminals for "zeroing out" the input off-set voltage. In many op-amps these terminals are internally connected to the load/source resistors/circuitry of the op-amps input transistors/FET's as such, this can be another source of "stray" voltage/currents that may effect functional operation. Hope this helps, Ralph Hersey [log in to unmask] -------------------------------------- Date: 8/21/96 12:03 PM From: David M Fulmer Topic: Surface moisture affecting operational amplifier output drift on a FR-4 multi-layer PCB. (board layup) - 1). component layer, 2). ground plane, 3). power plane, 4). solder side layer Question: When shielding the input pins of an operational amplifier with guard rings, is it recommended to expose the guard traces (solder over tin reflow), rather than covering them with solder mask ? *************************************************************************** * TechNet mail list is provided as a service by IPC using SmartList v3.05 * *************************************************************************** * To unsubscribe from this list at any time, send a message to: * * [log in to unmask] with <subject: unsubscribe> and no text. * *************************************************************************** ------------------ RFC822 Header Follows ------------------ Received: by quickmail.llnl.gov with SMTP;21 Aug 1996 12:02:36 -0700 Received: from ipc.org by simon.ipc.org via SMTP (940816.SGI.8.6.9/940406.SGI) id NAA05850; Wed, 21 Aug 1996 13:54:47 -0700 Resent-Date: Wed, 21 Aug 1996 13:54:47 -0700 Received: by ipc.org (Smail3.1.28.1 #2) id m0utHbX-0000RfC; Wed, 21 Aug 96 13:02 CDT Resent-Sender: [log in to unmask] Old-Return-Path: <[log in to unmask]> To: [log in to unmask], [log in to unmask] Date: Wed, 21 Aug 1996 14:06:29 PST Subject: Analog guard rings Message-ID: <[log in to unmask]> X-Mailer: Juno 1.00 X-Juno-Line-Breaks: 1,3-4,6,8 From: [log in to unmask] (David M Fulmer) Resent-Message-ID: <"G8v193.0.yZL.Ayq6o"@ipc> Resent-From: [log in to unmask] X-Mailing-List: <[log in to unmask]> archive/latest/5870 X-Loop: [log in to unmask] Precedence: list Resent-Sender: [log in to unmask] *************************************************************************** * TechNet mail list is provided as a service by IPC using SmartList v3.05 * *************************************************************************** * To unsubscribe from this list at any time, send a message to: * * [log in to unmask] with <subject: unsubscribe> and no text. * ***************************************************************************