Mail*Link(r) SMTP FWD>ASSY: PCB Repair - Plating Peter inquired about a customers concern about "stray" electrical fields when re-plating conductive patterns on printed board assemblies. Peter, both your customer's concern and your thoughts are correct. Some components (in particular some semiconductors) are may not tolerate 3-8 Vdc on I/O leads without a compariable operating voltage being applied to the component itself. Worse yet, some semiconductors will not tolerate reversed polarity voltages at all. They some MOS components and some bipolar components will be biased as a fully on diode or SCR and "burn up", unless current limited, at about 1 Vdc. Most bipolar base and integrated circuit inputs will break down with reversed voltages of about 5 Vdc. So yes your customer is right in their concern. Likewise you are correct in your approach to short-out by bussing with a very low resistance all conductive patterns that will or could become electrified, or as you mentioned to adequately insulate them with an insulative material. (Remember the definition for conductive patterns includes conductors, vias, components holes and printed contacts.) Make sure the shorting bus is as low a resistance as practical to ensure the current flow voltage drops in the bus are << than 300 mV, as ~300 mV is the turn-on voltage for germanium semiconductors and ~600 mV is the turn-on voltage for silicon semiconductors. And you're correct, if there are not voltage drops in the conductive patterns and your temporary plating bus, the components will see (for all practical purposes) no inducted voltages between conductive patterns. Hope this helps Ralph Hersey e-mail: [log in to unmask] -------------------------------------- Date: 6/3/96 11:29 AM From: [log in to unmask] A question re: board repair. When selectively re-plating a gold edge contact, using a procedure like IPC-R-700 4.2.3.1, a voltage is applied between a cathode and the (anode) plating swab. This voltage varies between 3V and 8V, depending on the plating or cleaning solution to be used. One of our customers has queried the possible damage such voltage might do the the components on his board. My thoughts are that the voltage and current will be confined to the plating area, and will not get to the components. To ensure this, either a) the gold fingers to be selectively plated should be temporarily "bussed" to keep them all at the same potential or b) if a single finger, then all surrounding area should be tape masked to prevent plating solutions and/or accidental voltage getting to it. Has anyone else considered this a potential problem? ((Excuse pun...)) Peter I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I Peter Swanson Oxfordshire, England INTERTRONICS [log in to unmask] Compuserve: 100120,3641 If it weren't for the last minute, nothing would ever get done. I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I ------------------ RFC822 Header Follows ------------------ Received: by quickmail.llnl.gov with SMTP;3 Jun 1996 11:29:23 -0700 Received: from ipc.org by simon.ipc.org via SMTP (940816.SGI.8.6.9/940406.SGI) id NAA09937; Mon, 3 Jun 1996 13:23:06 -0700 Resent-Date: Mon, 3 Jun 1996 13:23:06 -0700 Received: by ipc.org (Smail3.1.28.1 #2) id m0uQd6y-0000FfC; Mon, 3 Jun 96 12:08 CDT Resent-Sender: [log in to unmask] Old-Return-Path: <[log in to unmask]> Date: Mon, 03 Jun 1996 18:06:13 GMT From: [log in to unmask] (Peter Swanson) Reply-To: [log in to unmask] Message-Id: <[log in to unmask]> To: [log in to unmask] Subject: ASSY: PCB Repair - Plating X-Mailer: PCElm 1.10 Lines: 26 Resent-Message-ID: <"PAlX.0.Gb.olnin"@ipc> Resent-From: [log in to unmask] X-Mailing-List: <[log in to unmask]> archive/latest/4496 X-Loop: [log in to unmask] Precedence: list Resent-Sender: [log in to unmask]