As I read some of the comments regarding the open vias problem, I think there is some confusion which I'd like to clear up. Regarding tolerancing microvias with no bottom tolerance (i.e., they may plug shut), the plugging generally occurs during the solder levelling operation, not plating. Board fabricators must walk the tightrope between keeping holes open and not blowing too much solder off of surface mount pads when adjusting air knife placement and pressure. Another issue is using a small enogh drill diameter so that hole breakout is minimized. Board fabricators generally like some slack with vias in using a smaller drill size than the nominal callout of the via hole diameter in order to keep the hole in the pad. Aspect ratios (bd. thickness to dill size) of 7:1 or greater are not uncommon in volume environments these days. My company has just installed new PAL plating lines in our volume shops to meet such challenges. The PAL folks tell us that we should be able to plate boards with aspect ratios of 10:1! The fallout rate experienced by the original author strikes me as unusually high. One possible way that they might have escaped the E.T. net is if they were intermittent opens which may show up only when the board is flexed or stressed. Gary Ferrari's comments about supplying and requesting IPC-D-356 net lists should be well taken. This is an extra measure which should guarantee 100% electrical test on the part of the board fabricator. At the very least, it assures that the design intent and the Gerber supplied match. The bottom line is that I'd like to dispel any notion that allowing vias to plug shut causes a less reliable connect. Hole sections should be done by the board fabricator to get to the root of the real problem. Regards, Tom Coyle Field Services Engineer HADCO Corporation [log in to unmask]